forked from OSchip/llvm-project
286 lines
6.4 KiB
LLVM
286 lines
6.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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define i8 @sext_i1_to_i8(i1 %a) {
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; RV32I-LABEL: sext_i1_to_i8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: sub a0, zero, a0
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = sext i1 %a to i8
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ret i8 %1
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}
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define i16 @sext_i1_to_i16(i1 %a) {
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; RV32I-LABEL: sext_i1_to_i16:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: sub a0, zero, a0
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = sext i1 %a to i16
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ret i16 %1
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}
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define i32 @sext_i1_to_i32(i1 %a) {
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; RV32I-LABEL: sext_i1_to_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: sub a0, zero, a0
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = sext i1 %a to i32
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ret i32 %1
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}
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define i64 @sext_i1_to_i64(i1 %a) {
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; RV32I-LABEL: sext_i1_to_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: sub a0, zero, a0
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; RV32I-NEXT: addi a1, a0, 0
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = sext i1 %a to i64
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ret i64 %1
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}
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define i16 @sext_i8_to_i16(i8 %a) {
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; RV32I-LABEL: sext_i8_to_i16:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 24
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; RV32I-NEXT: srai a0, a0, 24
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = sext i8 %a to i16
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ret i16 %1
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}
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define i32 @sext_i8_to_i32(i8 %a) {
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; RV32I-LABEL: sext_i8_to_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 24
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; RV32I-NEXT: srai a0, a0, 24
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = sext i8 %a to i32
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ret i32 %1
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}
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define i64 @sext_i8_to_i64(i8 %a) {
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; RV32I-LABEL: sext_i8_to_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a1, a0, 24
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; RV32I-NEXT: srai a0, a1, 24
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; RV32I-NEXT: srai a1, a1, 31
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = sext i8 %a to i64
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ret i64 %1
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}
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define i32 @sext_i16_to_i32(i16 %a) {
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; RV32I-LABEL: sext_i16_to_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 16
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; RV32I-NEXT: srai a0, a0, 16
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = sext i16 %a to i32
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ret i32 %1
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}
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define i64 @sext_i16_to_i64(i16 %a) {
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; RV32I-LABEL: sext_i16_to_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a1, a0, 16
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; RV32I-NEXT: srai a0, a1, 16
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; RV32I-NEXT: srai a1, a1, 31
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = sext i16 %a to i64
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ret i64 %1
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}
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define i64 @sext_i32_to_i64(i32 %a) {
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; RV32I-LABEL: sext_i32_to_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srai a1, a0, 31
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = sext i32 %a to i64
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ret i64 %1
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}
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define i8 @zext_i1_to_i8(i1 %a) {
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; RV32I-LABEL: zext_i1_to_i8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = zext i1 %a to i8
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ret i8 %1
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}
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define i16 @zext_i1_to_i16(i1 %a) {
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; RV32I-LABEL: zext_i1_to_i16:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = zext i1 %a to i16
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ret i16 %1
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}
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define i32 @zext_i1_to_i32(i1 %a) {
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; RV32I-LABEL: zext_i1_to_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = zext i1 %a to i32
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ret i32 %1
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}
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define i64 @zext_i1_to_i64(i1 %a) {
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; RV32I-LABEL: zext_i1_to_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: addi a1, zero, 0
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = zext i1 %a to i64
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ret i64 %1
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}
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define i16 @zext_i8_to_i16(i8 %a) {
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; RV32I-LABEL: zext_i8_to_i16:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 255
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = zext i8 %a to i16
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ret i16 %1
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}
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define i32 @zext_i8_to_i32(i8 %a) {
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; RV32I-LABEL: zext_i8_to_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 255
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = zext i8 %a to i32
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ret i32 %1
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}
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define i64 @zext_i8_to_i64(i8 %a) {
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; RV32I-LABEL: zext_i8_to_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 255
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; RV32I-NEXT: addi a1, zero, 0
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = zext i8 %a to i64
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ret i64 %1
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}
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define i32 @zext_i16_to_i32(i16 %a) {
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; RV32I-LABEL: zext_i16_to_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 16
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; RV32I-NEXT: addi a1, a1, -1
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = zext i16 %a to i32
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ret i32 %1
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}
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define i64 @zext_i16_to_i64(i16 %a) {
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; RV32I-LABEL: zext_i16_to_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 16
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; RV32I-NEXT: addi a1, a1, -1
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: addi a1, zero, 0
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = zext i16 %a to i64
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ret i64 %1
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}
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define i64 @zext_i32_to_i64(i32 %a) {
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; RV32I-LABEL: zext_i32_to_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a1, zero, 0
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = zext i32 %a to i64
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ret i64 %1
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}
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; TODO: should the trunc tests explicitly ensure no code is generated before
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; jalr?
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define i1 @trunc_i8_to_i1(i8 %a) {
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; RV32I-LABEL: trunc_i8_to_i1:
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; RV32I: # %bb.0:
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = trunc i8 %a to i1
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ret i1 %1
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}
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define i1 @trunc_i16_to_i1(i16 %a) {
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; RV32I-LABEL: trunc_i16_to_i1:
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; RV32I: # %bb.0:
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = trunc i16 %a to i1
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ret i1 %1
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}
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define i1 @trunc_i32_to_i1(i32 %a) {
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; RV32I-LABEL: trunc_i32_to_i1:
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; RV32I: # %bb.0:
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = trunc i32 %a to i1
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ret i1 %1
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}
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define i1 @trunc_i64_to_i1(i64 %a) {
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; RV32I-LABEL: trunc_i64_to_i1:
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; RV32I: # %bb.0:
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = trunc i64 %a to i1
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ret i1 %1
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}
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define i8 @trunc_i16_to_i8(i16 %a) {
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; RV32I-LABEL: trunc_i16_to_i8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = trunc i16 %a to i8
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ret i8 %1
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}
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define i8 @trunc_i32_to_i8(i32 %a) {
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; RV32I-LABEL: trunc_i32_to_i8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = trunc i32 %a to i8
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ret i8 %1
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}
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define i8 @trunc_i64_to_i8(i64 %a) {
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; RV32I-LABEL: trunc_i64_to_i8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = trunc i64 %a to i8
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ret i8 %1
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}
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define i16 @trunc_i32_to_i16(i32 %a) {
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; RV32I-LABEL: trunc_i32_to_i16:
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; RV32I: # %bb.0:
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = trunc i32 %a to i16
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ret i16 %1
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}
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define i16 @trunc_i64_to_i16(i64 %a) {
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; RV32I-LABEL: trunc_i64_to_i16:
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; RV32I: # %bb.0:
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = trunc i64 %a to i16
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ret i16 %1
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}
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define i32 @trunc_i64_to_i32(i64 %a) {
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; RV32I-LABEL: trunc_i64_to_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = trunc i64 %a to i32
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ret i32 %1
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}
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