forked from OSchip/llvm-project
86 lines
3.8 KiB
LLVM
Executable File
86 lines
3.8 KiB
LLVM
Executable File
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -fast-isel-sink-local-values < %s -O0 -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s
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; ModuleID = 'mask_set.c'
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source_filename = "mask_set.c"
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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declare void @llvm.dbg.declare(metadata, metadata, metadata)
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; Function Attrs: nounwind uwtable
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declare i64 @calc_expected_mask_val(i8* %valp, i32 %el_size, i32 %length)
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; Function Attrs: nounwind uwtable
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declare i32 @check_mask16(i16 zeroext %res_mask, i16 zeroext %exp_mask, i8* %fname, i8* %input)
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; Function Attrs: nounwind uwtable
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define void @test_xmm(i32 %shift, i32 %mulp, <2 x i64> %a,i8* %arraydecay,i8* %fname){
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; CHECK-LABEL: test_xmm:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: subq $72, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 80
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; CHECK-NEXT: vpmovw2m %xmm0, %k0
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; CHECK-NEXT: movl $2, %esi
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; CHECK-NEXT: movl $8, %eax
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; CHECK-NEXT: movq %rdx, %rdi
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; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
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; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
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; CHECK-NEXT: kmovw %k0, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
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; CHECK-NEXT: callq _calc_expected_mask_val
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: movw %dx, %r8w
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; CHECK-NEXT: movzwl %r8w, %esi
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; CHECK-NEXT: kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k0 ## 2-byte Reload
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; CHECK-NEXT: kmovb %k0, %edi
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; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx ## 8-byte Reload
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; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx ## 8-byte Reload
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; CHECK-NEXT: callq _check_mask16
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; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
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; CHECK-NEXT: vpmovd2m %xmm0, %k0
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; CHECK-NEXT: kmovq %k0, %k1
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; CHECK-NEXT: kmovd %k0, %esi
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; CHECK-NEXT: movb %sil, %r9b
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; CHECK-NEXT: movzbl %r9b, %esi
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; CHECK-NEXT: movw %si, %r8w
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; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdi ## 8-byte Reload
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; CHECK-NEXT: movl $4, %esi
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; CHECK-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
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; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx ## 4-byte Reload
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; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
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; CHECK-NEXT: kmovw %k1, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
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; CHECK-NEXT: movw %r8w, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
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; CHECK-NEXT: callq _calc_expected_mask_val
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; CHECK-NEXT: movw %ax, %r8w
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; CHECK-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %r10w ## 2-byte Reload
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; CHECK-NEXT: movzwl %r10w, %edi
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; CHECK-NEXT: movzwl %r8w, %esi
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; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx ## 8-byte Reload
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; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx ## 8-byte Reload
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; CHECK-NEXT: callq _check_mask16
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; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
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; CHECK-NEXT: addq $72, %rsp
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; CHECK-NEXT: retq
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%d2 = bitcast <2 x i64> %a to <8 x i16>
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%m2 = call i8 @llvm.x86.avx512.cvtw2mask.128(<8 x i16> %d2)
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%conv7 = zext i8 %m2 to i16
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%call9 = call i64 @calc_expected_mask_val(i8* %arraydecay, i32 2, i32 8)
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%conv10 = trunc i64 %call9 to i16
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%call12 = call i32 @check_mask16(i16 zeroext %conv7, i16 zeroext %conv10, i8* %fname, i8* %arraydecay)
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%d3 = bitcast <2 x i64> %a to <4 x i32>
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%m3 = call i8 @llvm.x86.avx512.cvtd2mask.128(<4 x i32> %d3)
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%conv14 = zext i8 %m3 to i16
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%call16 = call i64 @calc_expected_mask_val(i8* %arraydecay, i32 4, i32 4)
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%conv17 = trunc i64 %call16 to i16
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%call19 = call i32 @check_mask16(i16 zeroext %conv14, i16 zeroext %conv17, i8* %fname, i8* %arraydecay)
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i8 @llvm.x86.avx512.cvtw2mask.128(<8 x i16>)
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; Function Attrs: nounwind readnone
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declare i8 @llvm.x86.avx512.cvtd2mask.128(<4 x i32>)
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