forked from OSchip/llvm-project
367 lines
12 KiB
C++
367 lines
12 KiB
C++
//===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements a TargetTransformInfo analysis pass specific to the
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/// X86 target machine. It uses the target's detailed information to provide
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/// more precise answers to certain TTI queries, while letting the target
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/// independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "x86tti"
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#include "X86.h"
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#include "X86TargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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// Declare the pass initialization routine locally as target-specific passes
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// don't havve a target-wide initialization entry point, and so we rely on the
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// pass constructor initialization.
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namespace llvm {
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void initializeX86TTIPass(PassRegistry &);
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}
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namespace {
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class X86TTI : public ImmutablePass, public TargetTransformInfo {
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const X86TargetMachine *TM;
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const X86Subtarget *ST;
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const X86TargetLowering *TLI;
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/// Estimate the overhead of scalarizing an instruction. Insert and Extract
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/// are set if the result needs to be inserted and/or extracted from vectors.
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unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
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public:
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X86TTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
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llvm_unreachable("This pass cannot be directly constructed");
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}
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X86TTI(const X86TargetMachine *TM)
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: ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
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TLI(TM->getTargetLowering()) {
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initializeX86TTIPass(*PassRegistry::getPassRegistry());
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}
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virtual void initializePass() {
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pushTTIStack(this);
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}
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virtual void finalizePass() {
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popTTIStack();
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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TargetTransformInfo::getAnalysisUsage(AU);
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}
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/// Pass identification.
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static char ID;
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/// Provide necessary pointer adjustments for the two base classes.
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virtual void *getAdjustedAnalysisPointer(const void *ID) {
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if (ID == &TargetTransformInfo::ID)
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return (TargetTransformInfo*)this;
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return this;
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}
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/// \name Scalar TTI Implementations
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/// @{
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virtual PopcntSupportKind getPopcntSupport(unsigned TyWidth) const;
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/// @}
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/// \name Vector TTI Implementations
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/// @{
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virtual unsigned getNumberOfRegisters(bool Vector) const;
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virtual unsigned getMaximumUnrollFactor() const;
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virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty) const;
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virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
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int Index, Type *SubTp) const;
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virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
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Type *Src) const;
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virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
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Type *CondTy) const;
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virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
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unsigned Index) const;
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virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
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unsigned Alignment,
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unsigned AddressSpace) const;
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/// @}
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};
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} // end anonymous namespace
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INITIALIZE_AG_PASS(X86TTI, TargetTransformInfo, "x86tti",
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"X86 Target Transform Info", true, true, false)
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char X86TTI::ID = 0;
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ImmutablePass *
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llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) {
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return new X86TTI(TM);
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}
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//===----------------------------------------------------------------------===//
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//
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// X86 cost model.
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//
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//===----------------------------------------------------------------------===//
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namespace {
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struct X86CostTblEntry {
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int ISD;
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MVT Type;
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unsigned Cost;
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};
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}
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static int
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FindInTable(const X86CostTblEntry *Tbl, unsigned len, int ISD, MVT Ty) {
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for (unsigned int i = 0; i < len; ++i)
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if (Tbl[i].ISD == ISD && Tbl[i].Type == Ty)
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return i;
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// Could not find an entry.
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return -1;
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}
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namespace {
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struct X86TypeConversionCostTblEntry {
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int ISD;
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MVT Dst;
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MVT Src;
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unsigned Cost;
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};
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}
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static int
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FindInConvertTable(const X86TypeConversionCostTblEntry *Tbl, unsigned len,
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int ISD, MVT Dst, MVT Src) {
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for (unsigned int i = 0; i < len; ++i)
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if (Tbl[i].ISD == ISD && Tbl[i].Src == Src && Tbl[i].Dst == Dst)
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return i;
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// Could not find an entry.
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return -1;
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}
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X86TTI::PopcntSupportKind X86TTI::getPopcntSupport(unsigned TyWidth) const {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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// TODO: Currently the __builtin_popcount() implementation using SSE3
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// instructions is inefficient. Once the problem is fixed, we should
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// call ST->hasSSE3() instead of ST->hasSSE4().
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return ST->hasSSE41() ? PSK_FastHardware : PSK_Software;
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}
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unsigned X86TTI::getNumberOfRegisters(bool Vector) const {
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if (ST->is64Bit())
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return 16;
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return 8;
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}
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unsigned X86TTI::getMaximumUnrollFactor() const {
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if (ST->isAtom())
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return 1;
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// Sandybridge and Haswell have multiple execution ports and pipelined
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// vector units.
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if (ST->hasAVX())
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return 4;
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return 2;
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}
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unsigned X86TTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty) const {
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// Legalize the type.
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std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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assert(ISD && "Invalid opcode");
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static const X86CostTblEntry AVX1CostTable[] = {
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// We don't have to scalarize unsupported ops. We can issue two half-sized
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// operations and we only need to extract the upper YMM half.
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// Two ops + 1 extract + 1 insert = 4.
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{ ISD::MUL, MVT::v8i32, 4 },
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{ ISD::SUB, MVT::v8i32, 4 },
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{ ISD::ADD, MVT::v8i32, 4 },
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{ ISD::MUL, MVT::v4i64, 4 },
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{ ISD::SUB, MVT::v4i64, 4 },
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{ ISD::ADD, MVT::v4i64, 4 },
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};
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// Look for AVX1 lowering tricks.
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if (ST->hasAVX()) {
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int Idx = FindInTable(AVX1CostTable, array_lengthof(AVX1CostTable), ISD,
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LT.second);
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if (Idx != -1)
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return LT.first * AVX1CostTable[Idx].Cost;
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}
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// Fallback to the default implementation.
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return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty);
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}
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unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
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Type *SubTp) const {
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// We only estimate the cost of reverse shuffles.
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if (Kind != SK_Reverse)
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return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
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std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
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unsigned Cost = 1;
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if (LT.second.getSizeInBits() > 128)
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Cost = 3; // Extract + insert + copy.
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// Multiple by the number of parts.
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return Cost * LT.first;
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}
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unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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assert(ISD && "Invalid opcode");
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EVT SrcTy = TLI->getValueType(Src);
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EVT DstTy = TLI->getValueType(Dst);
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if (!SrcTy.isSimple() || !DstTy.isSimple())
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return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
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static const X86TypeConversionCostTblEntry AVXConversionTbl[] = {
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{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
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{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
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{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
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{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
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{ ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 },
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{ ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1 },
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{ ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 },
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 },
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{ ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 },
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{ ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
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{ ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
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{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 6 },
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{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 9 },
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{ ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 },
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};
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if (ST->hasAVX()) {
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int Idx = FindInConvertTable(AVXConversionTbl,
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array_lengthof(AVXConversionTbl),
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ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT());
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if (Idx != -1)
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return AVXConversionTbl[Idx].Cost;
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}
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return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
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}
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unsigned X86TTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
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Type *CondTy) const {
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// Legalize the type.
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std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
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MVT MTy = LT.second;
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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assert(ISD && "Invalid opcode");
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static const X86CostTblEntry SSE42CostTbl[] = {
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{ ISD::SETCC, MVT::v2f64, 1 },
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{ ISD::SETCC, MVT::v4f32, 1 },
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{ ISD::SETCC, MVT::v2i64, 1 },
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{ ISD::SETCC, MVT::v4i32, 1 },
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{ ISD::SETCC, MVT::v8i16, 1 },
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{ ISD::SETCC, MVT::v16i8, 1 },
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};
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static const X86CostTblEntry AVX1CostTbl[] = {
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{ ISD::SETCC, MVT::v4f64, 1 },
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{ ISD::SETCC, MVT::v8f32, 1 },
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// AVX1 does not support 8-wide integer compare.
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{ ISD::SETCC, MVT::v4i64, 4 },
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{ ISD::SETCC, MVT::v8i32, 4 },
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{ ISD::SETCC, MVT::v16i16, 4 },
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{ ISD::SETCC, MVT::v32i8, 4 },
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};
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static const X86CostTblEntry AVX2CostTbl[] = {
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{ ISD::SETCC, MVT::v4i64, 1 },
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{ ISD::SETCC, MVT::v8i32, 1 },
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{ ISD::SETCC, MVT::v16i16, 1 },
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{ ISD::SETCC, MVT::v32i8, 1 },
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};
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if (ST->hasAVX2()) {
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int Idx = FindInTable(AVX2CostTbl, array_lengthof(AVX2CostTbl), ISD, MTy);
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if (Idx != -1)
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return LT.first * AVX2CostTbl[Idx].Cost;
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}
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if (ST->hasAVX()) {
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int Idx = FindInTable(AVX1CostTbl, array_lengthof(AVX1CostTbl), ISD, MTy);
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if (Idx != -1)
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return LT.first * AVX1CostTbl[Idx].Cost;
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}
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if (ST->hasSSE42()) {
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int Idx = FindInTable(SSE42CostTbl, array_lengthof(SSE42CostTbl), ISD, MTy);
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if (Idx != -1)
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return LT.first * SSE42CostTbl[Idx].Cost;
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}
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return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
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}
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unsigned X86TTI::getVectorInstrCost(unsigned Opcode, Type *Val,
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unsigned Index) const {
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assert(Val->isVectorTy() && "This must be a vector type");
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if (Index != -1U) {
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// Legalize the type.
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std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Val);
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// This type is legalized to a scalar type.
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if (!LT.second.isVector())
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return 0;
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// The type may be split. Normalize the index to the new type.
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unsigned Width = LT.second.getVectorNumElements();
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Index = Index % Width;
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// Floating point scalars are already located in index #0.
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if (Val->getScalarType()->isFloatingPointTy() && Index == 0)
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return 0;
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}
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return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
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}
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unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
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unsigned AddressSpace) const {
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// Legalize the type.
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std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
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assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
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"Invalid Opcode");
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// Each load/store unit costs 1.
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unsigned Cost = LT.first * 1;
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// On Sandybridge 256bit load/stores are double pumped
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// (but not on Haswell).
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if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2())
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Cost*=2;
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return Cost;
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}
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