forked from OSchip/llvm-project
369 lines
18 KiB
TableGen
369 lines
18 KiB
TableGen
//===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes FMA (Fused Multiply-Add) instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// FMA3 - Intel 3 operand Fused Multiply-Add instructions
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//===----------------------------------------------------------------------===//
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let Constraints = "$src1 = $dst" in {
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multiclass fma3p_rm<bits<8> opc, string OpcodeStr,
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PatFrag MemFrag128, PatFrag MemFrag256,
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ValueType OpVT128, ValueType OpVT256,
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SDPatternOperator Op = null_frag> {
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let isCommutable = 1 in
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def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst, (OpVT128 (Op VR128:$src2,
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VR128:$src1, VR128:$src3)))]>;
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let mayLoad = 1 in
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def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, f128mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst, (OpVT128 (Op VR128:$src2, VR128:$src1,
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(MemFrag128 addr:$src3))))]>;
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let isCommutable = 1 in
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def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR256:$dst, (OpVT256 (Op VR256:$src2, VR256:$src1,
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VR256:$src3)))]>, VEX_L;
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let mayLoad = 1 in
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def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, f256mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR256:$dst,
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(OpVT256 (Op VR256:$src2, VR256:$src1,
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(MemFrag256 addr:$src3))))]>, VEX_L;
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}
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} // Constraints = "$src1 = $dst"
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multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
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string OpcodeStr, string PackTy,
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PatFrag MemFrag128, PatFrag MemFrag256,
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SDNode Op, ValueType OpTy128, ValueType OpTy256> {
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defm r213 : fma3p_rm<opc213,
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!strconcat(OpcodeStr, !strconcat("213", PackTy)),
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MemFrag128, MemFrag256, OpTy128, OpTy256, Op>;
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let neverHasSideEffects = 1 in {
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defm r132 : fma3p_rm<opc132,
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!strconcat(OpcodeStr, !strconcat("132", PackTy)),
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MemFrag128, MemFrag256, OpTy128, OpTy256>;
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defm r231 : fma3p_rm<opc231,
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!strconcat(OpcodeStr, !strconcat("231", PackTy)),
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MemFrag128, MemFrag256, OpTy128, OpTy256>;
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} // neverHasSideEffects = 1
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}
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// Fused Multiply-Add
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let ExeDomain = SSEPackedSingle in {
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defm VFMADDPS : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", memopv4f32,
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memopv8f32, X86Fmadd, v4f32, v8f32>;
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defm VFMSUBPS : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", memopv4f32,
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memopv8f32, X86Fmsub, v4f32, v8f32>;
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defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps",
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memopv4f32, memopv8f32, X86Fmaddsub,
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v4f32, v8f32>;
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defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps",
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memopv4f32, memopv8f32, X86Fmsubadd,
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v4f32, v8f32>;
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}
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let ExeDomain = SSEPackedDouble in {
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defm VFMADDPD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", memopv2f64,
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memopv4f64, X86Fmadd, v2f64, v4f64>, VEX_W;
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defm VFMSUBPD : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", memopv2f64,
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memopv4f64, X86Fmsub, v2f64, v4f64>, VEX_W;
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defm VFMADDSUBPD : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd",
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memopv2f64, memopv4f64, X86Fmaddsub,
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v2f64, v4f64>, VEX_W;
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defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd",
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memopv2f64, memopv4f64, X86Fmsubadd,
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v2f64, v4f64>, VEX_W;
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}
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// Fused Negative Multiply-Add
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let ExeDomain = SSEPackedSingle in {
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defm VFNMADDPS : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", memopv4f32,
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memopv8f32, X86Fnmadd, v4f32, v8f32>;
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defm VFNMSUBPS : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", memopv4f32,
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memopv8f32, X86Fnmsub, v4f32, v8f32>;
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}
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let ExeDomain = SSEPackedDouble in {
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defm VFNMADDPD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", memopv2f64,
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memopv4f64, X86Fnmadd, v2f64, v4f64>, VEX_W;
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defm VFNMSUBPD : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd",
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memopv2f64, memopv4f64, X86Fnmsub, v2f64,
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v4f64>, VEX_W;
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}
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let Constraints = "$src1 = $dst" in {
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multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
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RegisterClass RC, ValueType OpVT, PatFrag mem_frag,
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SDPatternOperator OpNode = null_frag> {
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let isCommutable = 1 in
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def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
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let mayLoad = 1 in
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def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, x86memop:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src2, RC:$src1,
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(mem_frag addr:$src3))))]>;
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}
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multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr, Operand memop,
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ComplexPattern mem_cpat, Intrinsic IntId,
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RegisterClass RC> {
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let isCommutable = 1 in
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def r_Int : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst, (IntId VR128:$src2, VR128:$src1,
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VR128:$src3))]>;
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def m_Int : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, memop:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst,
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(IntId VR128:$src2, VR128:$src1, mem_cpat:$src3))]>;
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}
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} // Constraints = "$src1 = $dst"
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multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
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string OpStr, string PackTy, Intrinsic Int,
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SDNode OpNode, RegisterClass RC, ValueType OpVT,
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X86MemOperand x86memop, Operand memop, PatFrag mem_frag,
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ComplexPattern mem_cpat> {
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let neverHasSideEffects = 1 in {
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defm r132 : fma3s_rm<opc132, !strconcat(OpStr, !strconcat("132", PackTy)),
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x86memop, RC, OpVT, mem_frag>;
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defm r231 : fma3s_rm<opc231, !strconcat(OpStr, !strconcat("231", PackTy)),
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x86memop, RC, OpVT, mem_frag>;
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}
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defm r213 : fma3s_rm<opc213, !strconcat(OpStr, !strconcat("213", PackTy)),
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x86memop, RC, OpVT, mem_frag, OpNode>,
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fma3s_rm_int<opc213, !strconcat(OpStr, !strconcat("213", PackTy)),
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memop, mem_cpat, Int, RC>;
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}
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multiclass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231,
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string OpStr, Intrinsic IntF32, Intrinsic IntF64,
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SDNode OpNode> {
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defm SS : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", IntF32, OpNode,
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FR32, f32, f32mem, ssmem, loadf32, sse_load_f32>;
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defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", IntF64, OpNode,
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FR64, f64, f64mem, sdmem, loadf64, sse_load_f64>, VEX_W;
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}
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defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", int_x86_fma_vfmadd_ss,
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int_x86_fma_vfmadd_sd, X86Fmadd>, VEX_LIG;
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defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", int_x86_fma_vfmsub_ss,
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int_x86_fma_vfmsub_sd, X86Fmsub>, VEX_LIG;
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defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", int_x86_fma_vfnmadd_ss,
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int_x86_fma_vfnmadd_sd, X86Fnmadd>, VEX_LIG;
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defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", int_x86_fma_vfnmsub_ss,
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int_x86_fma_vfnmsub_sd, X86Fnmsub>, VEX_LIG;
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//===----------------------------------------------------------------------===//
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// FMA4 - AMD 4 operand Fused Multiply-Add instructions
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//===----------------------------------------------------------------------===//
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multiclass fma4s<bits<8> opc, string OpcodeStr, RegisterClass RC,
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X86MemOperand x86memop, ValueType OpVT, SDNode OpNode,
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PatFrag mem_frag> {
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let isCommutable = 1 in
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def rr : FMA4<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, MemOp4;
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def rm : FMA4<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, x86memop:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set RC:$dst, (OpNode RC:$src1, RC:$src2,
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(mem_frag addr:$src3)))]>, VEX_W, MemOp4;
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def mr : FMA4<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set RC:$dst,
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(OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>;
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// For disassembler
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let isCodeGenOnly = 1, hasSideEffects = 0 in
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def rr_REV : FMA4<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
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}
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multiclass fma4s_int<bits<8> opc, string OpcodeStr, Operand memop,
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ComplexPattern mem_cpat, Intrinsic Int> {
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let isCommutable = 1 in
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def rr_Int : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
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def rm_Int : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, memop:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst, (Int VR128:$src1, VR128:$src2,
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mem_cpat:$src3))]>, VEX_W, MemOp4;
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def mr_Int : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, memop:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>;
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}
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multiclass fma4p<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType OpVT128, ValueType OpVT256,
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PatFrag ld_frag128, PatFrag ld_frag256> {
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let isCommutable = 1 in
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def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(OpVT128 (OpNode VR128:$src1, VR128:$src2, VR128:$src3)))]>,
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VEX_W, MemOp4;
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def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, f128mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst, (OpNode VR128:$src1, VR128:$src2,
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(ld_frag128 addr:$src3)))]>, VEX_W, MemOp4;
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def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(OpNode VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
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let isCommutable = 1 in
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def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR256:$dst,
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(OpVT256 (OpNode VR256:$src1, VR256:$src2, VR256:$src3)))]>,
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VEX_W, MemOp4, VEX_L;
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def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, f256mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR256:$dst, (OpNode VR256:$src1, VR256:$src2,
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(ld_frag256 addr:$src3)))]>, VEX_W, MemOp4, VEX_L;
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def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, f256mem:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR256:$dst, (OpNode VR256:$src1,
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(ld_frag256 addr:$src2), VR256:$src3))]>, VEX_L;
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// For disassembler
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let isCodeGenOnly = 1, hasSideEffects = 0 in {
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def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
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def rrY_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
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VEX_L;
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} // isCodeGenOnly = 1
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}
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defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, X86Fmadd, loadf32>,
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fma4s_int<0x6A, "vfmaddss", ssmem, sse_load_f32,
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int_x86_fma_vfmadd_ss>;
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defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", FR64, f64mem, f64, X86Fmadd, loadf64>,
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fma4s_int<0x6B, "vfmaddsd", sdmem, sse_load_f64,
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int_x86_fma_vfmadd_sd>;
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defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", FR32, f32mem, f32, X86Fmsub, loadf32>,
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fma4s_int<0x6E, "vfmsubss", ssmem, sse_load_f32,
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int_x86_fma_vfmsub_ss>;
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defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", FR64, f64mem, f64, X86Fmsub, loadf64>,
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fma4s_int<0x6F, "vfmsubsd", sdmem, sse_load_f64,
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int_x86_fma_vfmsub_sd>;
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defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", FR32, f32mem, f32,
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X86Fnmadd, loadf32>,
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fma4s_int<0x7A, "vfnmaddss", ssmem, sse_load_f32,
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int_x86_fma_vfnmadd_ss>;
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defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", FR64, f64mem, f64,
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X86Fnmadd, loadf64>,
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fma4s_int<0x7B, "vfnmaddsd", sdmem, sse_load_f64,
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int_x86_fma_vfnmadd_sd>;
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defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", FR32, f32mem, f32,
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X86Fnmsub, loadf32>,
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fma4s_int<0x7E, "vfnmsubss", ssmem, sse_load_f32,
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int_x86_fma_vfnmsub_ss>;
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defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", FR64, f64mem, f64,
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X86Fnmsub, loadf64>,
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fma4s_int<0x7F, "vfnmsubsd", sdmem, sse_load_f64,
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int_x86_fma_vfnmsub_sd>;
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let ExeDomain = SSEPackedSingle in {
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defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86Fmadd, v4f32, v8f32,
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memopv4f32, memopv8f32>;
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defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32,
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memopv4f32, memopv8f32>;
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defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32,
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memopv4f32, memopv8f32>;
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defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32,
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memopv4f32, memopv8f32>;
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defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", X86Fmaddsub, v4f32, v8f32,
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memopv4f32, memopv8f32>;
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defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", X86Fmsubadd, v4f32, v8f32,
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memopv4f32, memopv8f32>;
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}
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let ExeDomain = SSEPackedDouble in {
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defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86Fmadd, v2f64, v4f64,
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memopv2f64, memopv4f64>;
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defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86Fmsub, v2f64, v4f64,
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memopv2f64, memopv4f64>;
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defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86Fnmadd, v2f64, v4f64,
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memopv2f64, memopv4f64>;
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defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86Fnmsub, v2f64, v4f64,
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memopv2f64, memopv4f64>;
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defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", X86Fmaddsub, v2f64, v4f64,
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memopv2f64, memopv4f64>;
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defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", X86Fmsubadd, v2f64, v4f64,
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memopv2f64, memopv4f64>;
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}
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