forked from OSchip/llvm-project
61 lines
2.1 KiB
C++
61 lines
2.1 KiB
C++
//===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp -----------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the InstructionSelector class.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#define DEBUG_TYPE "instructionselector"
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using namespace llvm;
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InstructionSelector::InstructionSelector() {}
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bool InstructionSelector::constrainSelectedInstRegOperands(
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MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) const {
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MachineBasicBlock &MBB = *I.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
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MachineOperand &MO = I.getOperand(OpI);
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// There's nothing to be done on non-register operands.
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if (!MO.isReg())
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continue;
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DEBUG(dbgs() << "Converting operand: " << MO << '\n');
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assert(MO.isReg() && "Unsupported non-reg operand");
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unsigned Reg = MO.getReg();
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// Physical registers don't need to be constrained.
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if (TRI.isPhysicalRegister(Reg))
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continue;
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// Register operands with a value of 0 (e.g. predicate operands) don't need
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// to be constrained.
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if (Reg == 0)
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continue;
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// If the operand is a vreg, we should constrain its regclass, and only
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// insert COPYs if that's impossible.
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// constrainOperandRegClass does that for us.
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MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
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Reg, OpI));
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}
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return true;
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}
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