llvm-project/llvm/lib/CodeGen
Andrew Kaylor a0a1164ce4 Add intrinsics for constrained floating point operations
This commit introduces a set of experimental intrinsics intended to prevent
optimizations that make assumptions about the rounding mode and floating point
exception behavior.  These intrinsics will later be extended to specify
flush-to-zero behavior.  More work is also required to model instruction
dependencies in machine code and to generate these instructions from clang
(when required by pragmas and/or command line options that are not currently
supported).

Differential Revision: https://reviews.llvm.org/D27028

llvm-svn: 293226
2017-01-26 23:27:59 +00:00
..
AsmPrinter DebugInfo: remove unused parameter from function. NFC. 2017-01-25 20:58:07 +00:00
GlobalISel GlobalISel: rework getOrCreateVReg to avoid double lookup. NFC. 2017-01-25 20:58:22 +00:00
MIRParser [MIRParser] Allow generic register specification on operand. 2017-01-20 00:29:59 +00:00
SelectionDAG Add intrinsics for constrained floating point operations 2017-01-26 23:27:59 +00:00
AggressiveAntiDepBreaker.cpp MachineFunction: Return reference for getFrameInfo(); NFC 2016-07-28 18:40:00 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp Use the range variant of find instead of unpacking begin/end 2016-08-11 22:21:41 +00:00
AllocationOrder.h Use the range variant of find instead of unpacking begin/end 2016-08-11 22:21:41 +00:00
Analysis.cpp [CodeGen] Further simplify returned call operand logic. NFC. 2017-01-03 21:42:43 +00:00
AntiDepBreaker.h
AtomicExpandPass.cpp Support expanding partial-word cmpxchg to full-word cmpxchg in AtomicExpandPass. 2016-06-17 18:11:48 +00:00
BasicTargetTransformInfo.cpp
BranchFolding.cpp BranchRelaxation: Recompute live-ins when splitting a block 2016-12-16 23:55:37 +00:00
BranchFolding.h BranchRelaxation: Recompute live-ins when splitting a block 2016-12-16 23:55:37 +00:00
BranchRelaxation.cpp BranchRelaxation: Recompute live-ins when splitting a block 2016-12-16 23:55:37 +00:00
BuiltinGCs.cpp
CMakeLists.txt New OptimizationRemarkEmitter pass for MIR 2017-01-25 23:20:33 +00:00
CalcSpillWeights.cpp CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
CallingConvLower.cpp [X86] Vectorcall Calling Convention - Adding CodeGen Complete Support 2016-12-21 08:31:45 +00:00
CodeGen.cpp RegAllocGreedy: Properly initialize this pass, so that -run-pass will work 2016-11-14 21:50:13 +00:00
CodeGenPrepare.cpp [CodeGenPrepare] Fix a typo in the comment. NFC. 2017-01-18 21:12:10 +00:00
CountingFunctionInserter.cpp Add a counter-function insertion pass 2016-09-01 09:42:39 +00:00
CriticalAntiDepBreaker.cpp MachineFunction: Return reference for getFrameInfo(); NFC 2016-07-28 18:40:00 +00:00
CriticalAntiDepBreaker.h
DFAPacketizer.cpp [Packetizer] Add debugging code to stop packetization after N instructions 2016-08-19 21:12:52 +00:00
DeadMachineInstructionElim.cpp CodeGen: Give MachineBasicBlock::reverse_iterator a handle to the current MI 2016-09-11 18:51:28 +00:00
DetectDeadLanes.cpp Implement LaneBitmask::any(), use it to replace !none(), NFCI 2016-12-16 19:11:56 +00:00
DwarfEHPrepare.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
EarlyIfConversion.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
EdgeBundles.cpp Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes. 2016-08-25 00:45:04 +00:00
ExecutionDepsFix.cpp LivePhysReg: Use reference instead of pointer in init(); NFC 2016-12-08 00:15:51 +00:00
ExpandISelPseudos.cpp CodeGen: Use MachineInstr& in ExpandISelPseudos, NFC 2016-06-30 23:09:39 +00:00
ExpandPostRAPseudos.cpp ExpandPostRAPseudos should transfer implicit uses, not only implicit defs 2016-07-15 22:31:14 +00:00
FaultMaps.cpp
FuncletLayout.cpp MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
GCMetadata.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
GCMetadataPrinter.cpp Reapply r276973 "Adjust Registry interface to not require plugins to export a registry" 2016-08-05 11:01:08 +00:00
GCRootLowering.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
GCStrategy.cpp Reapply r276973 "Adjust Registry interface to not require plugins to export a registry" 2016-08-05 11:01:08 +00:00
GlobalMerge.cpp Simplify code and address review comments (NFC) 2016-11-11 22:09:25 +00:00
IfConversion.cpp [IfConversion] Use reverse_iterator to simplify. NFC 2017-01-26 20:02:47 +00:00
ImplicitNullChecks.cpp [CodeGen] Rename MachineInstrBuilder::addOperand. NFC 2017-01-13 09:58:52 +00:00
InlineSpiller.cpp Fix for InlineSpiller accessing not updated dom tree base information. 2017-01-04 09:41:56 +00:00
InterferenceCache.cpp
InterferenceCache.h
InterleavedAccessPass.cpp Generalize strided store pattern in interleave access pass 2016-12-13 19:32:36 +00:00
IntrinsicLowering.cpp Create llvm.addressofreturnaddress intrinsic 2016-10-12 22:13:19 +00:00
LLVMBuild.txt Prune unused libdeps. 2016-12-08 15:28:02 +00:00
LLVMTargetMachine.cpp GlobalISel: Abort in ResetMachineFunctionPass if fallback isn't enabled 2017-01-13 23:46:11 +00:00
LatencyPriorityQueue.cpp Use the range variant of find instead of unpacking begin/end 2016-08-11 22:21:41 +00:00
LexicalScopes.cpp Rewrite loops to use range-based for. (NFC) 2016-09-28 17:31:17 +00:00
LiveDebugValues.cpp Teach LiveDebugValues about lexical scopes. 2016-09-28 17:51:14 +00:00
LiveDebugVariables.cpp [CodeGen] Rename MachineInstrBuilder::addOperand. NFC 2017-01-13 09:58:52 +00:00
LiveDebugVariables.h
LiveInterval.cpp Implement LaneBitmask::any(), use it to replace !none(), NFCI 2016-12-16 19:11:56 +00:00
LiveIntervalAnalysis.cpp LiveIntervalAnalysis: Calculate liveness even if a superreg is reserved. 2017-01-24 01:12:58 +00:00
LiveIntervalUnion.cpp Use the range variant of find instead of unpacking begin/end 2016-08-11 22:21:41 +00:00
LivePhysRegs.cpp BranchRelaxation: Recompute live-ins when splitting a block 2016-12-16 23:55:37 +00:00
LiveRangeCalc.cpp Treat segment [B, E) as not overlapping block with boundaries [A, B) 2017-01-18 23:12:19 +00:00
LiveRangeCalc.h Extract LaneBitmask into a separate type 2016-12-15 14:36:06 +00:00
LiveRangeEdit.cpp Implement LaneBitmask::any(), use it to replace !none(), NFCI 2016-12-16 19:11:56 +00:00
LiveRangeUtils.h CodeGen: Refactor renameDisconnectedComponents() as a pass 2016-05-31 22:38:06 +00:00
LiveRegMatrix.cpp Implement LaneBitmask::any(), use it to replace !none(), NFCI 2016-12-16 19:11:56 +00:00
LiveRegUnits.cpp LiveRegUnits: Add accumulateBackward() function 2017-01-21 02:21:04 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp Modify df_iterator to support post-order actions 2016-10-05 21:36:16 +00:00
LocalStackSlotAllocation.cpp Fix nondeterministic output in local stack slot alloc pass 2016-10-26 14:53:50 +00:00
LowLevelType.cpp GlobalISel: produce correct code for signext/zeroext ABI flags. 2016-09-21 12:57:45 +00:00
LowerEmuTLS.cpp
MIRPrinter.cpp CodeGen: Assert that liveness is up to date when reading block live-ins. 2017-01-05 20:01:19 +00:00
MIRPrinter.h
MIRPrintingPass.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
MachineBasicBlock.cpp [AMDGPU] Prevent spills before exec mask is restored 2017-01-20 00:44:31 +00:00
MachineBlockFrequencyInfo.cpp Turn cl::values() (for enum) from a vararg function to using C++ variadic template 2016-10-08 19:41:06 +00:00
MachineBlockPlacement.cpp Revert "CodeGen: Allow small copyable blocks to "break" the CFG." 2017-01-11 19:55:19 +00:00
MachineBranchProbabilityInfo.cpp Use the range variant of find/find_if instead of unpacking begin/end 2016-08-12 03:55:06 +00:00
MachineCSE.cpp [codegen] Add generic functions to skip debug values. 2016-12-16 11:10:26 +00:00
MachineCombiner.cpp machine combiner: fix pretty printer 2016-12-21 01:41:12 +00:00
MachineCopyPropagation.cpp MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
MachineDominanceFrontier.cpp
MachineDominators.cpp Revert "Do not verify dominator tree if it has no roots" 2017-01-25 17:15:48 +00:00
MachineFunction.cpp Move most EH from MachineModuleInfo to MachineFunction 2016-12-01 19:32:15 +00:00
MachineFunctionPass.cpp Reverted: Track validity of pass results 2017-01-15 10:23:18 +00:00
MachineFunctionPrinterPass.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
MachineInstr.cpp MachineInstr: Print name for subreg index in SUBREG_TO_REG 2017-01-09 21:38:10 +00:00
MachineInstrBundle.cpp CodeGen/Passes: Pass MachineFunction as functor arg; NFC 2016-10-24 23:23:02 +00:00
MachineLICM.cpp When instructions are hoisted out of loops by MachineLICM, remove their debug loc. 2016-12-02 00:37:57 +00:00
MachineLoopInfo.cpp New OptimizationRemarkEmitter pass for MIR 2017-01-25 23:20:33 +00:00
MachineModuleInfo.cpp Move most EH from MachineModuleInfo to MachineFunction 2016-12-01 19:32:15 +00:00
MachineModuleInfoImpls.cpp
MachineOptimizationRemarkEmitter.cpp New OptimizationRemarkEmitter pass for MIR 2017-01-25 23:20:33 +00:00
MachinePassRegistry.cpp
MachinePipeliner.cpp Add the DAG mutation interface to the software pipeliner 2016-12-22 19:21:20 +00:00
MachinePostDominators.cpp
MachineRegionInfo.cpp
MachineRegisterInfo.cpp GlobalISel: allow CodeGen to fallback on VReg type/class issues. 2016-11-08 20:39:03 +00:00
MachineSSAUpdater.cpp Retire llvm::alignOf in favor of C++11 alignof. 2016-10-20 15:02:18 +00:00
MachineScheduler.cpp Implement LaneBitmask::any(), use it to replace !none(), NFCI 2016-12-16 19:11:56 +00:00
MachineSink.cpp MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFC 2016-10-28 18:05:09 +00:00
MachineTraceMetrics.cpp [ADT] Change PostOrderIterator to use NodeRef. NFC. 2016-08-15 21:52:54 +00:00
MachineVerifier.cpp CodeGen: Assert that liveness is up to date when reading block live-ins. 2017-01-05 20:01:19 +00:00
OptimizePHIs.cpp CodeGen: Avoid dereferencing end() in OptimizePHIs::OptimizeBB 2016-08-17 00:43:59 +00:00
PHIElimination.cpp MachineFunction: Introduce NoPHIs property 2016-08-23 21:19:49 +00:00
PHIEliminationUtils.cpp Place the lowered phi instruction(s) before the DEBUG_VALUE entry 2016-09-16 14:07:29 +00:00
PHIEliminationUtils.h
ParallelCG.cpp Bitcode: Change module reader functions to return an llvm::Expected. 2016-11-13 07:00:17 +00:00
PatchableFunction.cpp [CodeGen] Rename MachineInstrBuilder::addOperand. NFC 2017-01-13 09:58:52 +00:00
PeepholeOptimizer.cpp PeepholeOptimizer: Do not replace SubregToReg(bitcast like) 2017-01-09 21:38:17 +00:00
PostRAHazardRecognizer.cpp CodeGen: Use MachineInstr& in PostRAHazardRecognizer, NFC 2016-07-01 00:50:29 +00:00
PostRASchedulerList.cpp MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
PreISelIntrinsicLowering.cpp [PM] Port PreISelIntrinsicLowering to the new PM 2016-06-24 20:13:42 +00:00
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp [thumb,framelowering] Reset NoVRegs in Thumb1FrameLowering::emitPrologue. 2017-01-18 15:01:22 +00:00
PseudoSourceValue.cpp
README.txt
RegAllocBase.cpp Timer: Track name and description. 2016-11-18 19:43:18 +00:00
RegAllocBase.h Timer: Track name and description. 2016-11-18 19:43:18 +00:00
RegAllocBasic.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
RegAllocFast.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
RegAllocGreedy.cpp New OptimizationRemarkEmitter pass for MIR 2017-01-25 23:20:33 +00:00
RegAllocPBQP.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
RegUsageInfoCollector.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
RegUsageInfoPropagate.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
RegisterClassInfo.cpp Add iterator_range<regclass_iterator> to {Target,MC}RegisterInfo, NFC 2017-01-25 19:29:04 +00:00
RegisterCoalescer.cpp Revert rL292621. Caused some internal build bot failures in apple. 2017-01-24 22:15:06 +00:00
RegisterCoalescer.h
RegisterPressure.cpp Implement LaneBitmask::any(), use it to replace !none(), NFCI 2016-12-16 19:11:56 +00:00
RegisterScavenging.cpp CodeGen: Add/Factor out LiveRegUnits class; NFCI 2017-01-20 00:16:14 +00:00
RegisterUsageInfo.cpp Move helpers into anonymous namespaces. NFC. 2016-08-06 11:13:10 +00:00
RenameIndependentSubregs.cpp Extract LaneBitmask into a separate type 2016-12-15 14:36:06 +00:00
ResetMachineFunctionPass.cpp GlobalISel: Abort in ResetMachineFunctionPass if fallback isn't enabled 2017-01-13 23:46:11 +00:00
SafeStack.cpp Test commit. 2016-10-17 19:09:19 +00:00
SafeStackColoring.cpp [safestack] Fix assertion failure in stack coloring. 2016-09-16 22:04:10 +00:00
SafeStackColoring.h StackColoring for SafeStack. 2016-06-29 20:37:43 +00:00
SafeStackLayout.cpp [safestack] Layout large allocas first to reduce fragmentation. 2016-08-02 23:21:30 +00:00
SafeStackLayout.h StackColoring for SafeStack. 2016-06-29 20:37:43 +00:00
ScheduleDAG.cpp [CodeGen] Implement the SUnit::print() method 2017-01-10 01:08:01 +00:00
ScheduleDAGInstrs.cpp Implement LaneBitmask::any(), use it to replace !none(), NFCI 2016-12-16 19:11:56 +00:00
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp Replace "fallthrough" comments with LLVM_FALLTHROUGH 2016-08-17 05:10:15 +00:00
ShadowStackGCLowering.cpp [tsan] Add support for C++ exceptions into TSan (call __tsan_func_exit during unwinding), LLVM part 2016-11-14 21:41:13 +00:00
ShrinkWrap.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
SjLjEHPrepare.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
SlotIndexes.cpp CodeGen: Use MachineInstr& in SlotIndexes.cpp, NFC 2016-07-01 15:08:52 +00:00
SpillPlacement.cpp Reapply r263460: [SpillPlacement] Fix a quadratic behavior in spill placement. 2016-05-19 22:40:37 +00:00
SpillPlacement.h Reapply r263460: [SpillPlacement] Fix a quadratic behavior in spill placement. 2016-05-19 22:40:37 +00:00
Spiller.h
SplitKit.cpp Implement LaneBitmask::any(), use it to replace !none(), NFCI 2016-12-16 19:11:56 +00:00
SplitKit.h Check proper live range in extendPHIRanges 2016-11-21 20:24:12 +00:00
StackColoring.cpp Move VariableDbgInfo from MachineModuleInfo to MachineFunction 2016-11-30 23:48:50 +00:00
StackMapLivenessAnalysis.cpp LivePhysReg: Use reference instead of pointer in init(); NFC 2016-12-08 00:15:51 +00:00
StackMaps.cpp [Stackmap] Added callsite counts to emitted function information. 2016-09-14 20:22:03 +00:00
StackProtector.cpp [CodeGen] stop short-circuiting the SSP code for sspstrong. 2016-09-20 21:30:01 +00:00
StackSlotColoring.cpp In the below scenario, we must be able to skip the a DBG_VALUE instruction and 2017-01-09 17:45:02 +00:00
TailDuplication.cpp Codegen: Tail-duplicate during placement. 2016-10-11 20:36:43 +00:00
TailDuplicator.cpp [MachineBlockPlacement] Don't make blocks "uneditable" 2016-12-15 05:08:57 +00:00
TargetFrameLoweringImpl.cpp Move most EH from MachineModuleInfo to MachineFunction 2016-12-01 19:32:15 +00:00
TargetInstrInfo.cpp [CodeGen] Rename MachineInstrBuilder::addOperand. NFC 2017-01-13 09:58:52 +00:00
TargetLoweringBase.cpp Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled." 2017-01-26 16:46:13 +00:00
TargetLoweringObjectFileImpl.cpp Revert "[COFF] Use 32-bit jump table entries in .rdata for Win64" 2016-12-29 17:07:10 +00:00
TargetOptionsImpl.cpp MachineFunction: Return reference for getFrameInfo(); NFC 2016-07-28 18:40:00 +00:00
TargetPassConfig.cpp TargetPassConfig: Rename DisablePostRA -> DisablePostRASched; NFC 2016-12-08 00:16:08 +00:00
TargetRegisterInfo.cpp Add iterator_range<regclass_iterator> to {Target,MC}RegisterInfo, NFC 2017-01-25 19:29:04 +00:00
TargetSchedule.cpp TargetSchedule: Do not consider subregister definitions as reads. 2016-08-24 02:32:29 +00:00
TargetSubtargetInfo.cpp TargetSubtargetInfo: Move implementation to lib/CodeGen; NFC 2016-11-22 22:09:03 +00:00
TwoAddressInstructionPass.cpp [CodeGen] Rename MachineInstrBuilder::addOperand. NFC 2017-01-13 09:58:52 +00:00
UnreachableBlockElim.cpp Modify df_iterator to support post-order actions 2016-10-05 21:36:16 +00:00
VirtRegMap.cpp Implement LaneBitmask::any(), use it to replace !none(), NFCI 2016-12-16 19:11:56 +00:00
WinEHPrepare.cpp [WinEH] Avoid holding references to BlockColor (DenseMap) entries while inserting new elements 2016-12-14 19:30:18 +00:00
XRayInstrumentation.cpp [CodeGen] Rename MachineInstrBuilder::addOperand. NFC 2017-01-13 09:58:52 +00:00

README.txt

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.