forked from OSchip/llvm-project
11001e1534
Use 'mark' nodes annotate a SIMD loop during ScheduleTransformation and skip parallelism checks. The buildbot shows the following compile/execution time changes: Compile time: Improvements Δ Previous Current σ …/gesummv -6.06% 0.2640 0.2480 0.0055 …/gemver -4.46% 0.4480 0.4280 0.0044 …/covariance -4.31% 0.8360 0.8000 0.0065 …/adi -3.23% 0.9920 0.9600 0.0065 …/doitgen -2.53% 0.9480 0.9240 0.0090 …/3mm -2.33% 1.0320 1.0080 0.0087 Execution time: Regressions Δ Previous Current σ …/viterbi 1.70% 5.1840 5.2720 0.0074 …/smallpt 1.06% 12.4920 12.6240 0.0040 Reviewed-by: Tobias Grosser <tobias@grosser.es> Differential Revision: http://reviews.llvm.org/D14491 llvm-svn: 261620 |
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.. | ||
2012-03-16-Empty-Domain.ll | ||
2012-04-16-Trivially-vectorizable-loops.ll | ||
2013-04-11-Empty-Domain-two.ll | ||
computeout.ll | ||
full_partial_tile_separation.ll | ||
line-tiling-2.ll | ||
line-tiling.ll | ||
one-dimensional-band.ll | ||
prevectorization-without-tiling.ll | ||
prevectorization.ll | ||
rectangular-tiling.ll |