forked from OSchip/llvm-project
60aa646441
This adds a G_ASSERT_SEXT opcode, similar to G_ASSERT_ZEXT. This instruction
signifies that an operation was already sign extended from a smaller type.
This is useful for functions with sign-extended parameters.
E.g.
```
define void @foo(i16 signext %x) {
...
}
```
This adds verifier, regbankselect, and instruction selection support for
G_ASSERT_SEXT equivalent to G_ASSERT_ZEXT.
Differential Revision: https://reviews.llvm.org/D96890
|
||
|---|---|---|
| .. | ||
| generic-vreg-undef-use.mir | ||
| live-ins-01.mir | ||
| live-ins-02.mir | ||
| live-ins-03.mir | ||
| test_copy.mir | ||
| test_copy_mismatch_types.mir | ||
| test_g_add.mir | ||
| test_g_addrspacecast.mir | ||
| test_g_assert_sext.mir | ||
| test_g_assert_sext_register_bank_class.mir | ||
| test_g_assert_zext.mir | ||
| test_g_assert_zext_register_bank_class.mir | ||
| test_g_bitcast.mir | ||
| test_g_brindirect_is_indirect_branch.mir | ||
| test_g_brjt.mir | ||
| test_g_brjt_is_indirect_branch.mir | ||
| test_g_build_vector.mir | ||
| test_g_build_vector_trunc.mir | ||
| test_g_concat_vectors.mir | ||
| test_g_constant.mir | ||
| test_g_dyn_stackalloc.mir | ||
| test_g_extract.mir | ||
| test_g_fcmp.mir | ||
| test_g_fconstant.mir | ||
| test_g_icmp.mir | ||
| test_g_insert.mir | ||
| test_g_intrinsic.mir | ||
| test_g_intrinsic_w_side_effects.mir | ||
| test_g_inttoptr.mir | ||
| test_g_jump_table.mir | ||
| test_g_load.mir | ||
| test_g_memcpy.mir | ||
| test_g_memset.mir | ||
| test_g_merge_values.mir | ||
| test_g_phi.mir | ||
| test_g_ptr_add.mir | ||
| test_g_ptrmask.mir | ||
| test_g_ptrtoint.mir | ||
| test_g_select.mir | ||
| test_g_sext_inreg.mir | ||
| test_g_sextload.mir | ||
| test_g_shuffle_vector.mir | ||
| test_g_store.mir | ||
| test_g_trunc.mir | ||
| test_g_zextload.mir | ||
| test_phis_precede_nonphis.mir | ||
| test_vector_reductions.mir | ||
| verifier-generic-extend-truncate.mir | ||
| verifier-generic-types-1.mir | ||
| verifier-generic-types-2.mir | ||
| verifier-implicit-virtreg-invalid-physreg-liveness.mir | ||
| verifier-phi-fail0.mir | ||
| verifier-phi.mir | ||
| verifier-pseudo-terminators.mir | ||
| verifier-statepoint.mir | ||
| verify-regbankselected.mir | ||
| verify-regops.mir | ||
| verify-selected.mir | ||