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llvm-project/llvm/test/CodeGen/MIR/AMDGPU
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madhur13490 3c297a2564 Make fixed-abi default for AMD HSA OS 
fixed-abi uses pre-defined and predictable
SGPR/VGPRs for passing arguments. This patch makes
this scheme default when HSA OS is specified in triple.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D96340
 		2021-02-19 15:05:25 +00:00
..
custom-pseudo-source-values.ll [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
expected-target-index-name.mir
…
intrinsics.mir
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invalid-target-index-operand.mir
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lit.local.cfg
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llc-target-cpu-attr-from-cmdline-ir.mir Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access"" 2020-11-11 14:40:14 +00:00
llc-target-cpu-attr-from-cmdline.mir Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access"" 2020-11-11 14:40:14 +00:00
load-store-opt-dlc.mir [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
load-store-opt-scc.mir [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
machine-function-info-dynlds-align-invalid-case.mir [amdgpu] Add codegen support for HIP dynamic shared memory. 2020-08-20 21:29:18 -04:00
machine-function-info-no-ir.mir Make fixed-abi default for AMD HSA OS 2021-02-19 15:05:25 +00:00
machine-function-info-register-parse-error1.mir [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
machine-function-info-register-parse-error2.mir [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
machine-function-info.ll AMDGPU: Add occupancy to serialized MachineFunctionInfo 2021-01-21 09:21:00 -05:00
mfi-frame-offset-reg-class.mir [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
mfi-parse-error-frame-offset-reg.mir [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
mfi-parse-error-scratch-rsrc-reg.mir [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
mfi-parse-error-stack-ptr-offset-reg.mir [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
mfi-scratch-rsrc-reg-reg-class.mir [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
mfi-stack-ptr-offset-reg-class.mir [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
mir-canon-multi.mir [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
mircanon-memoperands.mir [MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo) 2020-09-03 16:13:09 -04:00
parse-order-reserved-regs.mir [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
stack-id-assert.mir [MIR] Fix out of bounds access in MIRPrinter. 2020-10-29 14:35:06 +03:00
stack-id.mir
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subreg-def-is-not-ssa.mir MIR: Infer not-SSA for subregister defs 2020-08-27 16:56:16 -04:00
syncscopes.mir [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
target-flags.mir [AMDGPU] Fix offset for REL32_HI relocs 2020-09-02 10:55:55 +01:00
target-index-operands.mir [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00