llvm-project/llvm/test/CodeGen/MIR
madhur13490 3c297a2564 Make fixed-abi default for AMD HSA OS
fixed-abi uses pre-defined and predictable
SGPR/VGPRs for passing arguments. This patch makes
this scheme default when HSA OS is specified in triple.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D96340
2021-02-19 15:05:25 +00:00
..
AArch64 [MIRPrinter] Fix incorrect output of unnamed stack names 2020-12-28 18:01:40 +01:00
AMDGPU Make fixed-abi default for AMD HSA OS 2021-02-19 15:05:25 +00:00
ARM [ARM] Track epilogue instructions with FrameDestroy flag (NFC) 2020-03-18 13:32:59 +00:00
Generic MIR: Fix parser crash on syntax error on first character 2021-02-18 18:59:08 -05:00
Hexagon Reland D73534: [DebugInfo] Enable the debug entry values feature by default 2020-03-19 13:57:30 +01:00
Mips
NVPTX
PowerPC
WebAssembly
X86 [CodeGen] Try to make the print of memory operand alignment a little more user friendly. 2021-01-11 19:58:47 -08:00
README

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.