forked from OSchip/llvm-project
262 lines
12 KiB
LLVM
262 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+ssse3 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X86-SSE
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; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=AVX,AVX1,X86-AVX1
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; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=AVX,AVX512,X86-AVX512
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+ssse3 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X64-SSE
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=AVX,AVX1,X64-AVX1
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=AVX,AVX512,X64-AVX512
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define <4 x i32> @test_x86_ssse3_phadd_d_128(<4 x i32> %a0, <4 x i32> %a1) {
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; SSE-LABEL: test_x86_ssse3_phadd_d_128:
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; SSE: ## %bb.0:
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; SSE-NEXT: phaddd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x38,0x02,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX-LABEL: test_x86_ssse3_phadd_d_128:
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; AVX: ## %bb.0:
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; AVX-NEXT: vphaddd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x02,0xc1]
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; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32>, <4 x i32>) nounwind readnone
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define <8 x i16> @test_x86_ssse3_phadd_sw_128(<8 x i16> %a0, <8 x i16> %a1) {
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; SSE-LABEL: test_x86_ssse3_phadd_sw_128:
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; SSE: ## %bb.0:
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; SSE-NEXT: phaddsw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x38,0x03,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX-LABEL: test_x86_ssse3_phadd_sw_128:
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; AVX: ## %bb.0:
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; AVX-NEXT: vphaddsw %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x03,0xc1]
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; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
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define <8 x i16> @test_x86_ssse3_phadd_w_128(<8 x i16> %a0, <8 x i16> %a1) {
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; SSE-LABEL: test_x86_ssse3_phadd_w_128:
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; SSE: ## %bb.0:
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; SSE-NEXT: phaddw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x38,0x01,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX-LABEL: test_x86_ssse3_phadd_w_128:
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; AVX: ## %bb.0:
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; AVX-NEXT: vphaddw %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x01,0xc1]
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; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16>, <8 x i16>) nounwind readnone
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define <4 x i32> @test_x86_ssse3_phsub_d_128(<4 x i32> %a0, <4 x i32> %a1) {
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; SSE-LABEL: test_x86_ssse3_phsub_d_128:
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; SSE: ## %bb.0:
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; SSE-NEXT: phsubd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x38,0x06,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX-LABEL: test_x86_ssse3_phsub_d_128:
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; AVX: ## %bb.0:
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; AVX-NEXT: vphsubd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x06,0xc1]
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; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32>, <4 x i32>) nounwind readnone
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define <8 x i16> @test_x86_ssse3_phsub_sw_128(<8 x i16> %a0, <8 x i16> %a1) {
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; SSE-LABEL: test_x86_ssse3_phsub_sw_128:
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; SSE: ## %bb.0:
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; SSE-NEXT: phsubsw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x38,0x07,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX-LABEL: test_x86_ssse3_phsub_sw_128:
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; AVX: ## %bb.0:
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; AVX-NEXT: vphsubsw %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x07,0xc1]
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; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
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define <8 x i16> @test_x86_ssse3_phsub_w_128(<8 x i16> %a0, <8 x i16> %a1) {
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; SSE-LABEL: test_x86_ssse3_phsub_w_128:
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; SSE: ## %bb.0:
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; SSE-NEXT: phsubw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x38,0x05,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX-LABEL: test_x86_ssse3_phsub_w_128:
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; AVX: ## %bb.0:
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; AVX-NEXT: vphsubw %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x05,0xc1]
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; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16>, <8 x i16>) nounwind readnone
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define <8 x i16> @test_x86_ssse3_pmadd_ub_sw_128(<16 x i8> %a0, <16 x i8> %a1) {
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; SSE-LABEL: test_x86_ssse3_pmadd_ub_sw_128:
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; SSE: ## %bb.0:
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; SSE-NEXT: pmaddubsw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x38,0x04,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX1-LABEL: test_x86_ssse3_pmadd_ub_sw_128:
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; AVX1: ## %bb.0:
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; AVX1-NEXT: vpmaddubsw %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x04,0xc1]
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; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX512-LABEL: test_x86_ssse3_pmadd_ub_sw_128:
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; AVX512: ## %bb.0:
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; AVX512-NEXT: vpmaddubsw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x04,0xc1]
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; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<16 x i8> %a0, <16 x i8> %a1) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<16 x i8>, <16 x i8>) nounwind readnone
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; Make sure we don't commute this operation.
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define <8 x i16> @test_x86_ssse3_pmadd_ub_sw_128_load_op0(<16 x i8>* %ptr, <16 x i8> %a1) {
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; X86-SSE-LABEL: test_x86_ssse3_pmadd_ub_sw_128_load_op0:
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; X86-SSE: ## %bb.0:
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; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
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; X86-SSE-NEXT: movdqa (%eax), %xmm1 ## encoding: [0x66,0x0f,0x6f,0x08]
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; X86-SSE-NEXT: pmaddubsw %xmm0, %xmm1 ## encoding: [0x66,0x0f,0x38,0x04,0xc8]
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; X86-SSE-NEXT: movdqa %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x6f,0xc1]
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; X86-SSE-NEXT: retl ## encoding: [0xc3]
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;
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; X86-AVX1-LABEL: test_x86_ssse3_pmadd_ub_sw_128_load_op0:
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; X86-AVX1: ## %bb.0:
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; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
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; X86-AVX1-NEXT: vmovdqa (%eax), %xmm1 ## encoding: [0xc5,0xf9,0x6f,0x08]
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; X86-AVX1-NEXT: vpmaddubsw %xmm0, %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0x71,0x04,0xc0]
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; X86-AVX1-NEXT: retl ## encoding: [0xc3]
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;
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; X86-AVX512-LABEL: test_x86_ssse3_pmadd_ub_sw_128_load_op0:
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; X86-AVX512: ## %bb.0:
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; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
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; X86-AVX512-NEXT: vmovdqa (%eax), %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0x08]
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; X86-AVX512-NEXT: vpmaddubsw %xmm0, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x04,0xc0]
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; X86-AVX512-NEXT: retl ## encoding: [0xc3]
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;
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; X64-SSE-LABEL: test_x86_ssse3_pmadd_ub_sw_128_load_op0:
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; X64-SSE: ## %bb.0:
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; X64-SSE-NEXT: movdqa (%rdi), %xmm1 ## encoding: [0x66,0x0f,0x6f,0x0f]
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; X64-SSE-NEXT: pmaddubsw %xmm0, %xmm1 ## encoding: [0x66,0x0f,0x38,0x04,0xc8]
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; X64-SSE-NEXT: movdqa %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x6f,0xc1]
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; X64-SSE-NEXT: retq ## encoding: [0xc3]
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;
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; X64-AVX1-LABEL: test_x86_ssse3_pmadd_ub_sw_128_load_op0:
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; X64-AVX1: ## %bb.0:
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; X64-AVX1-NEXT: vmovdqa (%rdi), %xmm1 ## encoding: [0xc5,0xf9,0x6f,0x0f]
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; X64-AVX1-NEXT: vpmaddubsw %xmm0, %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0x71,0x04,0xc0]
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; X64-AVX1-NEXT: retq ## encoding: [0xc3]
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;
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; X64-AVX512-LABEL: test_x86_ssse3_pmadd_ub_sw_128_load_op0:
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; X64-AVX512: ## %bb.0:
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; X64-AVX512-NEXT: vmovdqa (%rdi), %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0x0f]
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; X64-AVX512-NEXT: vpmaddubsw %xmm0, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x04,0xc0]
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; X64-AVX512-NEXT: retq ## encoding: [0xc3]
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%a0 = load <16 x i8>, <16 x i8>* %ptr
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%res = call <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<16 x i8> %a0, <16 x i8> %a1) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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define <8 x i16> @test_x86_ssse3_pmul_hr_sw_128(<8 x i16> %a0, <8 x i16> %a1) {
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; SSE-LABEL: test_x86_ssse3_pmul_hr_sw_128:
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; SSE: ## %bb.0:
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; SSE-NEXT: pmulhrsw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x38,0x0b,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX1-LABEL: test_x86_ssse3_pmul_hr_sw_128:
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; AVX1: ## %bb.0:
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; AVX1-NEXT: vpmulhrsw %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x0b,0xc1]
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; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX512-LABEL: test_x86_ssse3_pmul_hr_sw_128:
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; AVX512: ## %bb.0:
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; AVX512-NEXT: vpmulhrsw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x0b,0xc1]
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; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
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define <16 x i8> @test_x86_ssse3_pshuf_b_128(<16 x i8> %a0, <16 x i8> %a1) {
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; SSE-LABEL: test_x86_ssse3_pshuf_b_128:
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; SSE: ## %bb.0:
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; SSE-NEXT: pshufb %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x38,0x00,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX1-LABEL: test_x86_ssse3_pshuf_b_128:
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; AVX1: ## %bb.0:
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; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x00,0xc1]
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; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX512-LABEL: test_x86_ssse3_pshuf_b_128:
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; AVX512: ## %bb.0:
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; AVX512-NEXT: vpshufb %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x00,0xc1]
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; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %res
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}
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declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) nounwind readnone
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define <16 x i8> @test_x86_ssse3_psign_b_128(<16 x i8> %a0, <16 x i8> %a1) {
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; SSE-LABEL: test_x86_ssse3_psign_b_128:
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; SSE: ## %bb.0:
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; SSE-NEXT: psignb %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x38,0x08,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX-LABEL: test_x86_ssse3_psign_b_128:
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; AVX: ## %bb.0:
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; AVX-NEXT: vpsignb %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x08,0xc1]
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; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %res
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}
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declare <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8>, <16 x i8>) nounwind readnone
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define <4 x i32> @test_x86_ssse3_psign_d_128(<4 x i32> %a0, <4 x i32> %a1) {
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; SSE-LABEL: test_x86_ssse3_psign_d_128:
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; SSE: ## %bb.0:
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; SSE-NEXT: psignd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x38,0x0a,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX-LABEL: test_x86_ssse3_psign_d_128:
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; AVX: ## %bb.0:
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; AVX-NEXT: vpsignd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x0a,0xc1]
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; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32>, <4 x i32>) nounwind readnone
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define <8 x i16> @test_x86_ssse3_psign_w_128(<8 x i16> %a0, <8 x i16> %a1) {
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; SSE-LABEL: test_x86_ssse3_psign_w_128:
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; SSE: ## %bb.0:
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; SSE-NEXT: psignw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x38,0x09,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX-LABEL: test_x86_ssse3_psign_w_128:
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; AVX: ## %bb.0:
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; AVX-NEXT: vpsignw %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x09,0xc1]
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; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <8 x i16> @llvm.x86.ssse3.psign.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.ssse3.psign.w.128(<8 x i16>, <8 x i16>) nounwind readnone
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