forked from OSchip/llvm-project
130 lines
4.6 KiB
LLVM
130 lines
4.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s
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; widen a v3i1 to v4i1 to do a vector load/store. We would previously
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; reconstruct the said v3i1 from the first element of the vector by filling all
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; the lanes of the vector with that first element, which was obviously wrong.
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; This was done in the type-legalizing of the DAG, when legalizing the load.
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; Function Attrs: argmemonly nounwind readonly
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declare <3 x i32> @llvm.masked.load.v3i32.p1v3i32(<3 x i32> addrspace(1)*, i32, <3 x i1>, <3 x i32>)
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; Function Attrs: argmemonly nounwind
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declare void @llvm.masked.store.v3i32.p1v3i32(<3 x i32>, <3 x i32> addrspace(1)*, i32, <3 x i1>)
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define <3 x i32> @masked_load_v3(i32 addrspace(1)*, <3 x i1>) {
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; CHECK-LABEL: masked_load_v3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: andb $1, %sil
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; CHECK-NEXT: andb $1, %dl
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; CHECK-NEXT: addb %dl, %dl
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; CHECK-NEXT: orb %sil, %dl
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; CHECK-NEXT: andb $1, %cl
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; CHECK-NEXT: shlb $2, %cl
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; CHECK-NEXT: orb %dl, %cl
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; CHECK-NEXT: testb $1, %cl
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; CHECK-NEXT: # implicit-def: $xmm0
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; CHECK-NEXT: jne .LBB0_1
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; CHECK-NEXT: # %bb.2: # %else
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; CHECK-NEXT: testb $2, %cl
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; CHECK-NEXT: jne .LBB0_3
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; CHECK-NEXT: .LBB0_4: # %else2
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; CHECK-NEXT: testb $4, %cl
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; CHECK-NEXT: jne .LBB0_5
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; CHECK-NEXT: .LBB0_6: # %else5
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB0_1: # %cond.load
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; CHECK-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; CHECK-NEXT: testb $2, %cl
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; CHECK-NEXT: je .LBB0_4
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; CHECK-NEXT: .LBB0_3: # %cond.load1
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; CHECK-NEXT: pinsrd $1, 4(%rdi), %xmm0
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; CHECK-NEXT: testb $4, %cl
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; CHECK-NEXT: je .LBB0_6
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; CHECK-NEXT: .LBB0_5: # %cond.load4
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; CHECK-NEXT: pinsrd $2, 8(%rdi), %xmm0
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; CHECK-NEXT: retq
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entry:
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%2 = bitcast i32 addrspace(1)* %0 to <3 x i32> addrspace(1)*
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%3 = call <3 x i32> @llvm.masked.load.v3i32.p1v3i32(<3 x i32> addrspace(1)* %2, i32 4, <3 x i1> %1, <3 x i32> undef)
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ret <3 x i32> %3
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}
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define void @masked_store4_v3(<3 x i32>, i32 addrspace(1)*, <3 x i1>) {
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; CHECK-LABEL: masked_store4_v3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: andb $1, %sil
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; CHECK-NEXT: andb $1, %dl
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; CHECK-NEXT: addb %dl, %dl
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; CHECK-NEXT: orb %sil, %dl
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; CHECK-NEXT: andb $1, %cl
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; CHECK-NEXT: shlb $2, %cl
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; CHECK-NEXT: orb %dl, %cl
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; CHECK-NEXT: testb $1, %cl
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; CHECK-NEXT: jne .LBB1_1
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; CHECK-NEXT: # %bb.2: # %else
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; CHECK-NEXT: testb $2, %cl
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; CHECK-NEXT: jne .LBB1_3
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; CHECK-NEXT: .LBB1_4: # %else2
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; CHECK-NEXT: testb $4, %cl
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; CHECK-NEXT: jne .LBB1_5
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; CHECK-NEXT: .LBB1_6: # %else4
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB1_1: # %cond.store
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; CHECK-NEXT: movss %xmm0, (%rdi)
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; CHECK-NEXT: testb $2, %cl
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; CHECK-NEXT: je .LBB1_4
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; CHECK-NEXT: .LBB1_3: # %cond.store1
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; CHECK-NEXT: extractps $1, %xmm0, 4(%rdi)
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; CHECK-NEXT: testb $4, %cl
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; CHECK-NEXT: je .LBB1_6
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; CHECK-NEXT: .LBB1_5: # %cond.store3
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; CHECK-NEXT: extractps $2, %xmm0, 8(%rdi)
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; CHECK-NEXT: retq
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entry:
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%3 = bitcast i32 addrspace(1)* %1 to <3 x i32> addrspace(1)*
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call void @llvm.masked.store.v3i32.p1v3i32(<3 x i32> %0, <3 x i32> addrspace(1)* %3, i32 4, <3 x i1> %2)
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ret void
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}
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define void @local_load_v3i1(i32 addrspace(1)* %out, i32 addrspace(1)* %in, <3 x i1>* %predicate_ptr) nounwind {
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; CHECK-LABEL: local_load_v3i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: movq %rdi, %r14
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; CHECK-NEXT: movb (%rdx), %al
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shrb %cl
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; CHECK-NEXT: andb $1, %cl
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: shrb $2, %dl
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; CHECK-NEXT: andb $1, %al
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; CHECK-NEXT: movzbl %al, %ebp
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; CHECK-NEXT: movzbl %dl, %r15d
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; CHECK-NEXT: movzbl %cl, %ebx
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; CHECK-NEXT: movq %rsi, %rdi
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; CHECK-NEXT: movl %ebp, %esi
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; CHECK-NEXT: movl %ebx, %edx
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; CHECK-NEXT: movl %r15d, %ecx
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; CHECK-NEXT: callq masked_load_v3@PLT
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; CHECK-NEXT: movq %r14, %rdi
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; CHECK-NEXT: movl %ebp, %esi
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; CHECK-NEXT: movl %ebx, %edx
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; CHECK-NEXT: movl %r15d, %ecx
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; CHECK-NEXT: callq masked_store4_v3@PLT
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; CHECK-NEXT: addq $8, %rsp
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: retq
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%predicate = load <3 x i1>, <3 x i1>* %predicate_ptr
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%load1 = call <3 x i32> @masked_load_v3(i32 addrspace(1)* %in, <3 x i1> %predicate)
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call void @masked_store4_v3(<3 x i32> %load1, i32 addrspace(1)* %out, <3 x i1> %predicate)
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ret void
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}
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