forked from OSchip/llvm-project
65 lines
2.7 KiB
LLVM
65 lines
2.7 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx512f -debug-only=isel < %s -o /dev/null 2>&1 | FileCheck %s
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; This tests the propagation of fast-math-flags from IR instructions to SDNodeFlags.
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; CHECK-LABEL: Initial selection DAG: %bb.0 'fmf_transfer:'
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; CHECK: t5: f32 = fadd nsz t2, t4
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; CHECK-NEXT: t6: f32 = fadd arcp t5, t4
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; CHECK-NEXT: t7: f32 = fadd nnan t6, t4
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; CHECK-NEXT: t8: f32 = fadd ninf t7, t4
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; CHECK-NEXT: t9: f32 = fadd contract t8, t4
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; CHECK-NEXT: t10: f32 = fadd afn t9, t4
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; CHECK-NEXT: t11: f32 = fadd reassoc t10, t4
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; CHECK-NEXT: t12: f32 = fadd nnan ninf nsz arcp contract afn reassoc t11, t4
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; CHECK: Optimized lowered selection DAG: %bb.0 'fmf_transfer:'
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define float @fmf_transfer(float %x, float %y) {
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%f1 = fadd nsz float %x, %y
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%f2 = fadd arcp float %f1, %y
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%f3 = fadd nnan float %f2, %y
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%f4 = fadd ninf float %f3, %y
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%f5 = fadd contract float %f4, %y
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%f6 = fadd afn float %f5, %y
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%f7 = fadd reassoc float %f6, %y
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%f8 = fadd fast float %f7, %y
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ret float %f8
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}
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; CHECK-LABEL: Optimized type-legalized selection DAG: %bb.0 'fmf_setcc:'
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; CHECK: t13: i8 = setcc nnan ninf nsz arcp contract afn reassoc t2, ConstantFP:f32<0.000000e+00>, setlt:ch
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define float @fmf_setcc(float %x, float %y) {
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%cmp = fcmp fast ult float %x, 0.0
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%ret = select i1 %cmp, float %x, float %y
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ret float %ret
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}
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; CHECK-LABEL: Initial selection DAG: %bb.0 'fmf_setcc_canon:'
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; CHECK: t14: i8 = setcc nnan ninf nsz arcp contract afn reassoc t2, ConstantFP:f32<0.000000e+00>, setgt:ch
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define float @fmf_setcc_canon(float %x, float %y) {
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%cmp = fcmp fast ult float 0.0, %x
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%ret = select i1 %cmp, float %x, float %y
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ret float %ret
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}
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declare <16 x float> @llvm.x86.avx512.vfmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i32)
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; Check that FMF are propagated twice: from IR to x86-specific node and from x86-specific node to generic node.
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; CHECK-LABEL: Initial selection DAG: %bb.0 'fmf_target_intrinsic:'
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; CHECK: v16f32 = llvm.x86.avx512.vfmadd.ps.512 ninf nsz TargetConstant:i64<{{.*}}>
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; CHECK: v16f32 = llvm.x86.avx512.vfmadd.ps.512 nsz TargetConstant:i64<{{.*}}>
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; CHECK-LABEL: Legalized selection DAG: %bb.0 'fmf_target_intrinsic:'
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; CHECK: v16f32 = fma ninf nsz t{{.*}}
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; CHECK: v16f32 = fma nsz t{{.*}}
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define <16 x float> @fmf_target_intrinsic(<16 x float> %a, <16 x float> %b, <16 x float> %c) nounwind {
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%t0 = tail call ninf nsz <16 x float> @llvm.x86.avx512.vfmadd.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %c, i32 4)
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%t1 = tail call nsz <16 x float> @llvm.x86.avx512.vfmadd.ps.512(<16 x float> %t0, <16 x float> %b, <16 x float> %c, i32 4)
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ret <16 x float> %t1
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}
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