llvm-project/llvm/test/CodeGen
Jingu Kang 73a196a11c Recommit "[AArch64] Split bitmask immediate of bitwise AND operation"
This reverts the revert commit f85d8a5bed
with bug fixes.

Original message:

    MOVi32imm + ANDWrr ==> ANDWri + ANDWri
    MOVi64imm + ANDXrr ==> ANDXri + ANDXri

    The mov pseudo instruction could be expanded to multiple mov instructions later.
    In this case, try to split the constant operand of mov instruction into two
    bitmask immediates. It makes only two AND instructions intead of multiple
    mov + and instructions.

    Added a peephole optimization pass on MIR level to implement it.

    Differential Revision: https://reviews.llvm.org/D109963
2021-09-28 15:26:29 +01:00
..
AArch64 Recommit "[AArch64] Split bitmask immediate of bitwise AND operation" 2021-09-28 15:26:29 +01:00
AMDGPU [AMDGPU] Change ASAN init/fini kernels linkage to external. 2021-09-27 11:50:37 -06:00
ARC [ARC] Improve code generated for i32 ADDC/ADDE and SUBC/SUBE 2021-09-10 13:04:08 -07:00
ARM Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
AVR
BPF BPF: make 32bit register spill with 64bit alignment 2021-09-20 21:00:25 -07:00
Generic Moved the test to X86 as it's x86 specific. 2021-08-31 14:48:29 -04:00
Hexagon [LiveIntervals] Repair subreg ranges in processTiedPairs 2021-09-28 08:10:16 +01:00
Inputs
Lanai [Lanai] implement wide immediate support 2021-09-10 10:54:43 +00:00
M68k [M68k][test] Migrate the remaining fixup and relaxation tests 2021-09-04 16:27:13 -07:00
MIR [Tests] Fix incorrect noalias metadata 2021-09-18 20:51:00 +02:00
MSP430 [llvm-readobj] Support dumping of MSP430 ELF attributes 2021-09-28 00:56:11 +03:00
Mips Fix tests defaulting to incorrect triples on AIX 2021-09-27 11:30:45 -04:00
NVPTX Fix tests defaulting to incorrect triples on AIX 2021-09-27 11:30:45 -04:00
PowerPC [PowerPC][NFC] Add test case in preparation for codegen change 2021-09-24 12:17:50 -05:00
RISCV [RISCV] Fold store of vmv.x.s to a vse with VL=1. 2021-09-27 09:54:46 -07:00
SPARC Fix tests defaulting to incorrect triples on AIX 2021-09-27 11:30:45 -04:00
SystemZ [LiveIntervals] Repair subreg ranges in processTiedPairs 2021-09-28 08:10:16 +01:00
Thumb Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
Thumb2 [ARM] Skip debug info in recomputeVPTBlockMask 2021-09-28 14:58:13 +01:00
VE
WebAssembly [WebAssembly] Add prototype relaxed SIMD fma/fms instructions 2021-09-23 11:01:36 -07:00
WinCFGuard
WinEH Fix SEH table addresses for Windows 2021-08-20 22:32:12 +03:00
X86 [LiveIntervals] Improve repair after convertToThreeAddress 2021-09-28 08:10:08 +01:00
XCore