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Jingu Kang 73a196a11c Recommit "[AArch64] Split bitmask immediate of bitwise AND operation" 
This reverts the revert commit f85d8a5bed
with bug fixes.

Original message:

    MOVi32imm + ANDWrr ==> ANDWri + ANDWri
    MOVi64imm + ANDXrr ==> ANDXri + ANDXri

    The mov pseudo instruction could be expanded to multiple mov instructions later.
    In this case, try to split the constant operand of mov instruction into two
    bitmask immediates. It makes only two AND instructions intead of multiple
    mov + and instructions.

    Added a peephole optimization pass on MIR level to implement it.

    Differential Revision: https://reviews.llvm.org/D109963
 		2021-09-28 15:26:29 +01:00
..
Analysis Recommit "[Test] Add more tests with cycled phis" 2021-09-28 19:36:47 +07:00
Assembler [ThinLTO] Add noRecurse and noUnwind thinlink function attribute propagation 2021-09-27 12:28:07 -07:00
Bindings
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Bitcode [ThinLTO] Add noRecurse and noUnwind thinlink function attribute propagation 2021-09-27 12:28:07 -07:00
BugPoint
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CodeGen Recommit "[AArch64] Split bitmask immediate of bitwise AND operation" 2021-09-28 15:26:29 +01:00
DebugInfo [DebugInfo] Emit DW_TAG_namelist and DW_TAG_namelist_item 2021-09-28 14:40:58 +05:30
Demangle
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Examples [ORC] Temporarily remove the lljit-with-remote-debugging test. 2021-09-12 18:52:30 +10:00
ExecutionEngine [MCJIT] This test shouldn't require an unwind table. 2021-09-26 14:14:41 -07:00
Feature
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FileCheck [FileCheck] Use StringRef for MatchRegexp to fix crash. 2021-09-01 14:27:14 +02:00
Instrumentation [hwasan] also omit safe mem[cpy|mov|set]. 2021-09-22 11:08:27 +01:00
Integer
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JitListener
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LTO Resolve {GlobalValue,GloalIndirectSymol}::getBaseObject confusion 2021-09-23 09:23:35 -07:00
Linker Copy Elementtype Attribute to IR at Link step 2021-09-07 11:41:43 -07:00
MC [llvm] Replace tab with spaces in one test 2021-09-23 15:34:01 -04:00
MachineVerifier Revert @llvm.isnan intrinsic patchset. 2021-09-02 13:53:56 +03:00
Object
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ObjectYAML [WebAssembly] Convert to new "dylink.0" section format 2021-09-12 05:30:38 -07:00
Other [ModuleInlinerWrapperPass] Do some naive printing of wrapped pipeline with -print-pipeline-passes 2021-09-23 09:54:42 +02:00
SafepointIRVerifier
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Support
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SymbolRewriter
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TableGen [TableGen] Allow targets to entirely ignore Psets for registers 2021-09-23 23:07:35 -04:00
ThinLTO/X86 [ThinLTO] Add noRecurse and noUnwind thinlink function attribute propagation 2021-09-27 12:28:07 -07:00
Transforms [SLP]Improve vectorization of phi nodes by trying wider vectors. 2021-09-28 07:20:36 -07:00
Unit
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Verifier [Verifier] Verify scoped noalias metadata 2021-09-20 18:27:28 +02:00
YAMLParser
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tools [llvm-readobj] Support dumping of MSP430 ELF attributes 2021-09-28 00:56:11 +03:00
.clang-format
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CMakeLists.txt
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TestRunner.sh
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lit.cfg.py Add extra check for llvm::Any::TypeId visibility 2021-09-15 08:32:55 +02:00
lit.site.cfg.py.in Add extra check for llvm::Any::TypeId visibility 2021-09-15 08:32:55 +02:00