Daniel Sanders a3134fae17 [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. ... Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883		2015-06-27 15:39:19 +00:00
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abiflags.s	[mips] Add MipsOptionRecord abstraction and use it to implement .reginfo/.MIPS.options	2014-07-21 13:30:55 +00:00
invalid-mips32r2.s	[mips] Marked the DI/EI instruction aliases as MIPS32r2	2014-10-16 15:23:52 +00:00
invalid-mips64r2-xfail.s	[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them	2014-05-13 11:45:36 +00:00
invalid-mips64r2.s	[MIPS]Multiple and add instructions for Mips are currently available in mips32r2/mips64r2 and later but should also be available in mips4, mips5, and mips64. This patch fixes the requested features and updates the corresponding test files.	2015-02-25 15:24:37 +00:00
valid-xfail.s	[MIPS]Multiple and add instructions for Mips are currently available in mips32r2/mips64r2 and later but should also be available in mips4, mips5, and mips64. This patch fixes the requested features and updates the corresponding test files.	2015-02-25 15:24:37 +00:00
valid.s	[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.	2015-06-27 15:39:19 +00:00