llvm-project/llvm/test/CodeGen/MIR
Matt Arsenault 75cf30918f AMDGPU: Assume f32 denormals are enabled by default
This will likely introduce catastrophic performance regressions on
older subtargets, but should be correct. A follow up change will
remove the old fp32-denormals subtarget features, and switch to using
the new denormal-fp-math/denormal-fp-math-f32 attributes. Frontends
should be making sure to add the denormal-fp-math-f32 attribute when
appropriate to avoid performance regressions.
2020-04-02 17:17:12 -04:00
..
AArch64 [llvm][MIRVRegNamer] Avoid collisions across constant pool indices. 2020-03-10 01:13:20 -04:00
AMDGPU AMDGPU: Assume f32 denormals are enabled by default 2020-04-02 17:17:12 -04:00
ARM [ARM] Track epilogue instructions with FrameDestroy flag (NFC) 2020-03-18 13:32:59 +00:00
Generic [llvm][MIRVRegNamerUtils] Adding hashing on CImm / FPImm MachineOperands. 2019-12-16 18:25:04 -05:00
Hexagon Reland D73534: [DebugInfo] Enable the debug entry values feature by default 2020-03-19 13:57:30 +01:00
Mips [MIParser] Set RegClassOrRegBank during instruction parsing 2019-10-22 14:25:37 +00:00
NVPTX
PowerPC [PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPC 2019-09-13 14:18:36 +00:00
WebAssembly [WebAssembly] Fix tests missed in rL374235 2019-10-09 23:06:38 +00:00
X86 Reland D73534: [DebugInfo] Enable the debug entry values feature by default 2020-03-19 13:57:30 +01:00
README

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.