forked from OSchip/llvm-project
a655393f17
The MVE architecture has the idea of "beats", where a vector instruction can be executed over several ticks of the architecture. This adds a similar system into the Arm backend cost model, multiplying the cost of all vector instructions by a factor. This factor essentially becomes the expected difference between scalar code and vector code, on average. MVE Vector instructions can also overlap so the a true cost of them is often lower. But equally scalar instructions can in some situations be dual issued, or have other optimisations such as unrolling or make use of dsp instructions. The default is chosen as 2. This should not prevent vectorisation is a most cases (as the vector instructions will still be doing at least 4 times the work), but it will help prevent over vectorising in cases where the benefits are less likely. This adds things so far to the obvious places in ARMTargetTransformInfo, and updates a few related costs like not treating float instructions as cost 2 just because they are floats. Differential Revision: https://reviews.llvm.org/D66005 llvm-svn: 368733 |
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| .. | ||
| AliasSet | ||
| AssumptionCache | ||
| BasicAA | ||
| BlockFrequencyInfo | ||
| BranchProbabilityInfo | ||
| CFLAliasAnalysis | ||
| CallGraph | ||
| ConstantFolding | ||
| CostModel | ||
| Delinearization | ||
| DemandedBits | ||
| DependenceAnalysis | ||
| DivergenceAnalysis | ||
| DominanceFrontier | ||
| Dominators | ||
| GlobalsModRef | ||
| IVUsers | ||
| LazyCallGraph | ||
| LazyValueAnalysis | ||
| LegacyDivergenceAnalysis | ||
| Lint | ||
| LoopAccessAnalysis | ||
| LoopCacheAnalysis/PowerPC | ||
| LoopInfo | ||
| MemoryDependenceAnalysis | ||
| MemorySSA | ||
| MustExecute | ||
| PhiValues | ||
| PostDominators | ||
| ProfileSummary | ||
| RegionInfo | ||
| ScalarEvolution | ||
| ScopedNoAliasAA | ||
| StackSafetyAnalysis | ||
| TypeBasedAliasAnalysis | ||
| ValueTracking | ||
| alias-analysis-uses.ll | ||