Thomas Lively 72c628e835 Reland "[WebAssembly] Emulate v128.const efficiently"" ... This reverts commit 432e4e56d3, which reverted 542523a61a. Two issues from the original commit have been fixed. First, MSVC does not like when std::array is initialized with only single braces, so this commit switches to using the more portable double braces. Second, there was a subtle endianness bug that prevented the original commit from working correctly on big-endian machines, which has been fixed by switching to using endianness-agnostic bit twiddling instead of type punning. Differential Revision: https://reviews.llvm.org/D88773		2020-10-13 04:36:59 +00:00
..
AArch64	[AArch64] Add tests for 128-bit shift variations.	2020-10-12 14:48:58 -07:00
AMDGPU	[AMDGPU] Update LiveVariables in convertToThreeAddress()	2020-10-13 08:12:20 +08:00
ARC	[ARC] Update brcc test.	2020-08-28 17:07:25 -07:00
ARM	Reland "[SCEV] Model ptrtoint(SCEVUnknown) cast not as unknown, but as zext/trunc/self of SCEVUnknown"	2020-10-12 23:02:55 +03:00
AVR	[AVR] fix interrupt stack pointer restoration	2020-10-01 18:52:13 +13:00
BPF	[BPF] Make BPFAbstractMemberAccessPass required	2020-10-09 11:26:37 -07:00
Generic	[llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics.	2020-10-07 10:36:44 -07:00
Hexagon	[Hexagon] Replace HexagonISD::VSPLAT with ISD::SPLAT_VECTOR	2020-10-10 19:49:47 -05:00
Inputs	…
Lanai	…
MIR	Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access"	2020-09-29 15:33:34 +02:00
MSP430	…
Mips	[DAG][ARM][MIPS][RISCV] Improve funnel shift promotion to use 'double shift' patterns	2020-10-12 14:11:02 +01:00
NVPTX	…
PowerPC	[NFC] Move PPC strict-fp MIR test to dedicated file	2020-10-12 10:40:19 +08:00
RISCV	[DAG][ARM][MIPS][RISCV] Improve funnel shift promotion to use 'double shift' patterns	2020-10-12 14:11:02 +01:00
SPARC	[Sparc] Remove cast that truncates immediate operands to 32 bits.	2020-10-02 20:14:55 -04:00
SystemZ	[SystemZ] Use LA instead of AGR in eliminateFrameIndex().	2020-10-09 13:06:33 +02:00
Thumb	…
Thumb2	[ARM] Attempt to make Tail predication / RDA more resilient to empty blocks	2020-10-10 14:50:25 +01:00
VE	[VE] Support copysign math function	2020-10-12 21:06:19 +09:00
WebAssembly	Reland "[WebAssembly] Emulate v128.const efficiently""	2020-10-13 04:36:59 +00:00
WinCFGuard	Revert "[CFGuard] Add address-taken IAT tables and delay-load support"	2020-10-01 11:29:54 -07:00
WinEH	…
X86	[llc] -filetype=null: don't create .null if -o is not specified	2020-10-12 17:28:59 -07:00
XCore	…