forked from OSchip/llvm-project
71 lines
2.3 KiB
C++
71 lines
2.3 KiB
C++
//===-- VEISelDAGToDAG.cpp - A dag to dag inst selector for VE ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the VE target.
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//
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//===----------------------------------------------------------------------===//
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#include "VETargetMachine.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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/// VEDAGToDAGISel - VE specific code to select VE machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class VEDAGToDAGISel : public SelectionDAGISel {
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/// Subtarget - Keep a pointer to the VE Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const VESubtarget *Subtarget;
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public:
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explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(tm) {}
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bool runOnMachineFunction(MachineFunction &MF) override {
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Subtarget = &MF.getSubtarget<VESubtarget>();
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return SelectionDAGISel::runOnMachineFunction(MF);
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}
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void Select(SDNode *N) override;
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StringRef getPassName() const override {
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return "VE DAG->DAG Pattern Instruction Selection";
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}
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// Include the pieces autogenerated from the target description.
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#include "VEGenDAGISel.inc"
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};
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} // end anonymous namespace
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void VEDAGToDAGISel::Select(SDNode *N) {
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SDLoc dl(N);
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if (N->isMachineOpcode()) {
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N->setNodeId(-1);
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return; // Already selected.
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}
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SelectCode(N);
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}
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/// createVEISelDag - This pass converts a legalized DAG into a
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/// VE-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createVEISelDag(VETargetMachine &TM) {
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return new VEDAGToDAGISel(TM);
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}
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