llvm-project/llvm/lib/Target/SystemZ
Fangrui Song 8e8a75ad50 [TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true
Except AMDGPU/R600RegisterInfo (a bunch of MIR tests seem to have
problems), every target overrides it with true. PostMachineScheduler
requires livein information. Not providing it can cause assertion
failures in ScheduleDAGInstrs::addSchedBarrierDeps().
2020-01-19 14:20:37 -08:00
..
AsmParser CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
Disassembler CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
MCTargetDesc CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
TargetInfo CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
CMakeLists.txt [SystemZ] Merge the SystemZExpandPseudo pass into SystemZPostRewrite. 2019-09-16 07:29:37 +00:00
LLVMBuild.txt
README.txt
SystemZ.h [SystemZ] Bugfix and improve the handling of CC values. 2019-12-20 10:20:23 -08:00
SystemZ.td
SystemZAsmPrinter.cpp CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
SystemZAsmPrinter.h [SystemZ] Add support for fentry. 2019-09-03 11:21:12 +00:00
SystemZCallingConv.cpp
SystemZCallingConv.h [SystemZ] Add GHC calling convention 2019-11-04 13:45:51 +01:00
SystemZCallingConv.td [SystemZ] Add GHC calling convention 2019-11-04 13:45:51 +01:00
SystemZConstantPoolValue.cpp
SystemZConstantPoolValue.h
SystemZElimCompare.cpp [FPEnv] Invert sense of MIFlag::FPExcept flag 2020-01-10 15:34:50 +01:00
SystemZFeatures.td [SystemZ] Add support for new cpu architecture - arch13 2019-07-12 18:13:16 +00:00
SystemZFrameLowering.cpp [SystemZ] Don't allow CL option -mpacked-stack with -mbackchain. 2020-01-03 12:26:54 -08:00
SystemZFrameLowering.h [SystemZ] Implement the packed stack layout 2019-12-12 10:26:03 -08:00
SystemZHazardRecognizer.cpp
SystemZHazardRecognizer.h
SystemZISelDAGToDAG.cpp [SystemZ] Fix matching another pattern for nxgrk (PR44496) 2020-01-09 19:06:22 +01:00
SystemZISelLowering.cpp GlobalISel: Preserve load/store metadata in IRTranslator 2020-01-16 13:49:43 -05:00
SystemZISelLowering.h GlobalISel: Preserve load/store metadata in IRTranslator 2020-01-16 13:49:43 -05:00
SystemZInstrBuilder.h
SystemZInstrDFP.td
SystemZInstrFP.td [SystemZ][FPEnv] Back-end support for STRICT_[SU]INT_TO_FP 2019-12-17 18:24:05 +01:00
SystemZInstrFormats.td [SystemZ] Add a mapping from "select register" to "load on condition" (2-addr). 2019-12-20 10:44:58 -08:00
SystemZInstrHFP.td
SystemZInstrInfo.cpp [SystemZ] Bugfix and improve the handling of CC values. 2019-12-20 10:20:23 -08:00
SystemZInstrInfo.h [SystemZ] Bugfix and improve the handling of CC values. 2019-12-20 10:20:23 -08:00
SystemZInstrInfo.td [SystemZ] Add a mapping from "select register" to "load on condition" (2-addr). 2019-12-20 10:44:58 -08:00
SystemZInstrSystem.td
SystemZInstrVector.td [SystemZ][FPEnv] Enable strict vector FP extends/truncations 2019-12-20 15:36:56 +01:00
SystemZLDCleanup.cpp
SystemZLongBranch.cpp Fix uninitialized variable warning. NFCI. 2019-11-13 14:40:21 +00:00
SystemZMCInstLower.cpp
SystemZMCInstLower.h
SystemZMachineFunctionInfo.cpp
SystemZMachineFunctionInfo.h [SystemZ] Implement the packed stack layout 2019-12-12 10:26:03 -08:00
SystemZMachineScheduler.cpp Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each 2019-10-19 01:31:09 +00:00
SystemZMachineScheduler.h
SystemZOperands.td [SystemZ] Improve verification of MachineOperands. 2019-12-16 09:51:54 -08:00
SystemZOperators.td [SystemZ][FPEnv] Enable strict vector FP extends/truncations 2019-12-20 15:36:56 +01:00
SystemZPatterns.td [FPEnv] Constrained FCmp intrinsics 2019-12-07 11:28:39 +01:00
SystemZPostRewrite.cpp [SystemZ] Merge the SystemZExpandPseudo pass into SystemZPostRewrite. 2019-09-16 07:29:37 +00:00
SystemZProcessors.td [SystemZ] Support z15 processor name 2019-09-20 23:04:45 +00:00
SystemZRegisterInfo.cpp [SystemZ] Add a mapping from "select register" to "load on condition" (2-addr). 2019-12-20 10:44:58 -08:00
SystemZRegisterInfo.h [TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true 2020-01-19 14:20:37 -08:00
SystemZRegisterInfo.td
SystemZSchedule.td [SystemZ] Support z15 processor name 2019-09-20 23:04:45 +00:00
SystemZScheduleZ13.td [SystemZ] Support vector load/store alignment hints 2019-06-19 14:20:00 +00:00
SystemZScheduleZ14.td [SystemZ] Support vector load/store alignment hints 2019-06-19 14:20:00 +00:00
SystemZScheduleZ15.td [SystemZ] Support z15 processor name 2019-09-20 23:04:45 +00:00
SystemZScheduleZ196.td
SystemZScheduleZEC12.td
SystemZSelectionDAGInfo.cpp Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics" 2019-09-19 16:26:14 +00:00
SystemZSelectionDAGInfo.h
SystemZShortenInst.cpp [SystemZ] Add a mapping from "select register" to "load on condition" (2-addr). 2019-12-20 10:44:58 -08:00
SystemZSubtarget.cpp [SystemZ] Add support for new cpu architecture - arch13 2019-07-12 18:13:16 +00:00
SystemZSubtarget.h [SystemZ] Add support for new cpu architecture - arch13 2019-07-12 18:13:16 +00:00
SystemZTDC.cpp [IR] Split out target specific intrinsic enums into separate headers 2019-12-11 18:02:14 -08:00
SystemZTargetMachine.cpp CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
SystemZTargetMachine.h
SystemZTargetTransformInfo.cpp Rename TTI::getIntImmCost for instructions and intrinsics 2019-12-11 18:00:20 -08:00
SystemZTargetTransformInfo.h Rename TTI::getIntImmCost for instructions and intrinsics 2019-12-11 18:00:20 -08:00

README.txt

//===---------------------------------------------------------------------===//
// Random notes about and ideas for the SystemZ backend.
//===---------------------------------------------------------------------===//

The initial backend is deliberately restricted to z10.  We should add support
for later architectures at some point.

--

If an inline asm ties an i32 "r" result to an i64 input, the input
will be treated as an i32, leaving the upper bits uninitialised.
For example:

define void @f4(i32 *%dst) {
  %val = call i32 asm "blah $0", "=r,0" (i64 103)
  store i32 %val, i32 *%dst
  ret void
}

from CodeGen/SystemZ/asm-09.ll will use LHI rather than LGHI.
to load 103.  This seems to be a general target-independent problem.

--

The tuning of the choice between LOAD ADDRESS (LA) and addition in
SystemZISelDAGToDAG.cpp is suspect.  It should be tweaked based on
performance measurements.

--

There is no scheduling support.

--

We don't use the BRANCH ON INDEX instructions.

--

We only use MVC, XC and CLC for constant-length block operations.
We could extend them to variable-length operations too,
using EXECUTE RELATIVE LONG.

MVCIN, MVCLE and CLCLE may be worthwhile too.

--

We don't use CUSE or the TRANSLATE family of instructions for string
operations.  The TRANSLATE ones are probably more difficult to exploit.

--

We don't take full advantage of builtins like fabsl because the calling
conventions require f128s to be returned by invisible reference.

--

ADD LOGICAL WITH SIGNED IMMEDIATE could be useful when we need to
produce a carry.  SUBTRACT LOGICAL IMMEDIATE could be useful when we
need to produce a borrow.  (Note that there are no memory forms of
ADD LOGICAL WITH CARRY and SUBTRACT LOGICAL WITH BORROW, so the high
part of 128-bit memory operations would probably need to be done
via a register.)

--

We don't use ICM, STCM, or CLM.

--

We don't use ADD (LOGICAL) HIGH, SUBTRACT (LOGICAL) HIGH,
or COMPARE (LOGICAL) HIGH yet.

--

DAGCombiner doesn't yet fold truncations of extended loads.  Functions like:

    unsigned long f (unsigned long x, unsigned short *y)
    {
      return (x << 32) | *y;
    }

therefore end up as:

        sllg    %r2, %r2, 32
        llgh    %r0, 0(%r3)
        lr      %r2, %r0
        br      %r14

but truncating the load would give:

        sllg    %r2, %r2, 32
        lh      %r2, 0(%r3)
        br      %r14

--

Functions like:

define i64 @f1(i64 %a) {
  %and = and i64 %a, 1
  ret i64 %and
}

ought to be implemented as:

        lhi     %r0, 1
        ngr     %r2, %r0
        br      %r14

but two-address optimizations reverse the order of the AND and force:

        lhi     %r0, 1
        ngr     %r0, %r2
        lgr     %r2, %r0
        br      %r14

CodeGen/SystemZ/and-04.ll has several examples of this.

--

Out-of-range displacements are usually handled by loading the full
address into a register.  In many cases it would be better to create
an anchor point instead.  E.g. for:

define void @f4a(i128 *%aptr, i64 %base) {
  %addr = add i64 %base, 524288
  %bptr = inttoptr i64 %addr to i128 *
  %a = load volatile i128 *%aptr
  %b = load i128 *%bptr
  %add = add i128 %a, %b
  store i128 %add, i128 *%aptr
  ret void
}

(from CodeGen/SystemZ/int-add-08.ll) we load %base+524288 and %base+524296
into separate registers, rather than using %base+524288 as a base for both.

--

Dynamic stack allocations round the size to 8 bytes and then allocate
that rounded amount.  It would be simpler to subtract the unrounded
size from the copy of the stack pointer and then align the result.
See CodeGen/SystemZ/alloca-01.ll for an example.

--

If needed, we can support 16-byte atomics using LPQ, STPQ and CSDG.

--

We might want to model all access registers and use them to spill
32-bit values.

--

We might want to use the 'overflow' condition of eg. AR to support
llvm.sadd.with.overflow.i32 and related instructions - the generated code
for signed overflow check is currently quite bad.  This would improve
the results of using -ftrapv.