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llvm-project/llvm/test/CodeGen
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Mitch Phillips 72a3d8597d Revert "[MachinePipeliner] Improve the TargetInstrInfo API analyzeLoop/reduceLoopCount" 
This commit broke the ASan buildbot. See comments in rL372376 for more
information.

This reverts commit 15e27b0b6d.

llvm-svn: 372425
 		2019-09-20 20:25:16 +00:00
..
AArch64 [MTE] Handle MTE instructions in AArch64LoadStoreOptimizer. 2019-09-20 17:36:27 +00:00
AMDGPU Remove assert from MachineLoop::getLoopPredecessor() 2019-09-20 15:26:10 +00:00
ARC
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ARM Remove the obsolete BlockByRefStruct flag from LLVM IR 2019-09-18 22:38:56 +00:00
AVR
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BPF [BPF] Permit all user instructed offset relocatiions 2019-09-18 03:49:07 +00:00
Generic Revert "Reland "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."" 2019-09-10 10:39:09 +00:00
Hexagon Revert "[MachinePipeliner] Improve the TargetInstrInfo API analyzeLoop/reduceLoopCount" 2019-09-20 20:25:16 +00:00
Inputs
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Lanai [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
MIR Add a missing space in a MIR parser error message 2019-09-20 14:41:41 +00:00
MSP430
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Mips [MIPS] For vectors, select `add %x, C` as `sub %x, -C` if it results in inline immediate 2019-09-18 19:34:41 +00:00
NVPTX
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PowerPC [NFC][PowerPC] Fast-isel VSX support test 2019-09-19 18:18:18 +00:00
RISCV [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
SPARC [test] Fix tests when run on windows after SVN r369426. NFC. 2019-08-20 20:58:02 +00:00
SystemZ [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
Thumb [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
Thumb2 [ARM] Fix CTTZ not generating correct instructions MVE 2019-09-20 15:03:44 +00:00
WebAssembly [WebAssembly] Restore defaults for stores per memop 2019-09-18 23:18:16 +00:00
WinCFGuard
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WinEH [Windows] Replace TrapUnreachable with an int3 insertion pass 2019-09-09 23:04:25 +00:00
X86 [X86] Use timm in MMX pinsrw/pextrw isel patterns. Add missing test cases. 2019-09-20 06:00:35 +00:00
XCore
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