forked from OSchip/llvm-project
81 lines
2.9 KiB
LLVM
81 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver1 | FileCheck %s
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; clang -Oz -c test1.cpp -emit-llvm -S -o
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; Verify that we generate shld insruction when we are optimizing for size,
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; even for X86_64 processors that are known to have poor latency double
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; precision shift instructions.
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; uint64_t lshift10(uint64_t a, uint64_t b)
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; {
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; return (a << 10) | (b >> 54);
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; }
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; Function Attrs: minsize nounwind readnone uwtable
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define i64 @_Z8lshift10mm(i64 %a, i64 %b) #0 {
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; CHECK-LABEL: _Z8lshift10mm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: shldq $10, %rsi, %rax
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; CHECK-NEXT: retq
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entry:
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%shl = shl i64 %a, 10
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%shr = lshr i64 %b, 54
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%or = or i64 %shr, %shl
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ret i64 %or
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}
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attributes #0 = { minsize nounwind readnone uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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; clang -Os -c test2.cpp -emit-llvm -S
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; Verify that we generate shld insruction when we are optimizing for size,
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; even for X86_64 processors that are known to have poor latency double
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; precision shift instructions.
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; uint64_t lshift11(uint64_t a, uint64_t b)
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; {
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; return (a << 11) | (b >> 53);
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; }
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; Function Attrs: nounwind optsize readnone uwtable
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define i64 @_Z8lshift11mm(i64 %a, i64 %b) #1 {
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; CHECK-LABEL: _Z8lshift11mm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: shldq $11, %rsi, %rax
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; CHECK-NEXT: retq
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entry:
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%shl = shl i64 %a, 11
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%shr = lshr i64 %b, 53
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%or = or i64 %shr, %shl
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ret i64 %or
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}
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attributes #1 = { nounwind optsize readnone uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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; clang -O2 -c test2.cpp -emit-llvm -S
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; Verify that we do not generate shld insruction when we are not optimizing
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; for size for X86_64 processors that are known to have poor latency double
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; precision shift instructions.
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; uint64_t lshift12(uint64_t a, uint64_t b)
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; {
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; return (a << 12) | (b >> 52);
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; }
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; Function Attrs: nounwind optsize readnone uwtable
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define i64 @_Z8lshift12mm(i64 %a, i64 %b) #2 {
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; CHECK-LABEL: _Z8lshift12mm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: shlq $12, %rdi
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; CHECK-NEXT: shrq $52, %rsi
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; CHECK-NEXT: leaq (%rsi,%rdi), %rax
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; CHECK-NEXT: retq
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entry:
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%shl = shl i64 %a, 12
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%shr = lshr i64 %b, 52
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%or = or i64 %shr, %shl
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ret i64 %or
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}
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attributes #2= { nounwind readnone uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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