forked from OSchip/llvm-project
172 lines
7.6 KiB
LLVM
172 lines
7.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse3 -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86,SSE,X86-SSE
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; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86,AVX,X86-AVX,AVX1,X86-AVX1
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; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86,AVX,X86-AVX,AVX512,X86-AVX512
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse3 -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64,SSE,X64-SSE
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64,AVX,X64-AVX,AVX1,X64-AVX1
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64,AVX,X64-AVX,AVX512,X64-AVX512
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define <2 x double> @test_x86_sse3_addsub_pd(<2 x double> %a0, <2 x double> %a1) {
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; SSE-LABEL: test_x86_sse3_addsub_pd:
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; SSE: ## %bb.0:
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; SSE-NEXT: addsubpd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xd0,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX-LABEL: test_x86_sse3_addsub_pd:
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; AVX: ## %bb.0:
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; AVX-NEXT: vaddsubpd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xd0,0xc1]
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; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
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ret <2 x double> %res
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}
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declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwind readnone
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define <4 x float> @test_x86_sse3_addsub_ps(<4 x float> %a0, <4 x float> %a1) {
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; SSE-LABEL: test_x86_sse3_addsub_ps:
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; SSE: ## %bb.0:
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; SSE-NEXT: addsubps %xmm1, %xmm0 ## encoding: [0xf2,0x0f,0xd0,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX-LABEL: test_x86_sse3_addsub_ps:
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; AVX: ## %bb.0:
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; AVX-NEXT: vaddsubps %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0xd0,0xc1]
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; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind readnone
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define <2 x double> @test_x86_sse3_hadd_pd(<2 x double> %a0, <2 x double> %a1) {
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; SSE-LABEL: test_x86_sse3_hadd_pd:
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; SSE: ## %bb.0:
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; SSE-NEXT: haddpd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x7c,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX-LABEL: test_x86_sse3_hadd_pd:
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; AVX: ## %bb.0:
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; AVX-NEXT: vhaddpd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x7c,0xc1]
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; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
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ret <2 x double> %res
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}
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declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>) nounwind readnone
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define <4 x float> @test_x86_sse3_hadd_ps(<4 x float> %a0, <4 x float> %a1) {
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; SSE-LABEL: test_x86_sse3_hadd_ps:
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; SSE: ## %bb.0:
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; SSE-NEXT: haddps %xmm1, %xmm0 ## encoding: [0xf2,0x0f,0x7c,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX-LABEL: test_x86_sse3_hadd_ps:
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; AVX: ## %bb.0:
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; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x7c,0xc1]
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; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>) nounwind readnone
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define <2 x double> @test_x86_sse3_hsub_pd(<2 x double> %a0, <2 x double> %a1) {
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; SSE-LABEL: test_x86_sse3_hsub_pd:
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; SSE: ## %bb.0:
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; SSE-NEXT: hsubpd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x7d,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX-LABEL: test_x86_sse3_hsub_pd:
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; AVX: ## %bb.0:
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; AVX-NEXT: vhsubpd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x7d,0xc1]
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; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
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ret <2 x double> %res
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}
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declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
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define <4 x float> @test_x86_sse3_hsub_ps(<4 x float> %a0, <4 x float> %a1) {
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; SSE-LABEL: test_x86_sse3_hsub_ps:
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; SSE: ## %bb.0:
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; SSE-NEXT: hsubps %xmm1, %xmm0 ## encoding: [0xf2,0x0f,0x7d,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX-LABEL: test_x86_sse3_hsub_ps:
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; AVX: ## %bb.0:
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; AVX-NEXT: vhsubps %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x7d,0xc1]
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; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
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define <16 x i8> @test_x86_sse3_ldu_dq(i8* %a0) {
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; X86-SSE-LABEL: test_x86_sse3_ldu_dq:
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; X86-SSE: ## %bb.0:
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; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
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; X86-SSE-NEXT: lddqu (%eax), %xmm0 ## encoding: [0xf2,0x0f,0xf0,0x00]
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; X86-SSE-NEXT: retl ## encoding: [0xc3]
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;
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; X86-AVX-LABEL: test_x86_sse3_ldu_dq:
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; X86-AVX: ## %bb.0:
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; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
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; X86-AVX-NEXT: vlddqu (%eax), %xmm0 ## encoding: [0xc5,0xfb,0xf0,0x00]
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; X86-AVX-NEXT: retl ## encoding: [0xc3]
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;
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; X64-SSE-LABEL: test_x86_sse3_ldu_dq:
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; X64-SSE: ## %bb.0:
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; X64-SSE-NEXT: lddqu (%rdi), %xmm0 ## encoding: [0xf2,0x0f,0xf0,0x07]
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; X64-SSE-NEXT: retq ## encoding: [0xc3]
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;
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; X64-AVX-LABEL: test_x86_sse3_ldu_dq:
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; X64-AVX: ## %bb.0:
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; X64-AVX-NEXT: vlddqu (%rdi), %xmm0 ## encoding: [0xc5,0xfb,0xf0,0x07]
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; X64-AVX-NEXT: retq ## encoding: [0xc3]
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%res = call <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %a0) ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %res
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}
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declare <16 x i8> @llvm.x86.sse3.ldu.dq(i8*) nounwind readonly
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; Make sure instructions with no AVX equivalents, but are associated with SSEX feature flags still work
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define void @monitor(i8* %P, i32 %E, i32 %H) nounwind {
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; X86-LABEL: monitor:
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; X86: ## %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x08]
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ## encoding: [0x8b,0x54,0x24,0x0c]
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; X86-NEXT: monitor ## encoding: [0x0f,0x01,0xc8]
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; X86-NEXT: retl ## encoding: [0xc3]
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;
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; X64-LABEL: monitor:
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; X64: ## %bb.0:
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; X64-NEXT: movl %esi, %ecx ## encoding: [0x89,0xf1]
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; X64-NEXT: movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
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; X64-NEXT: monitor ## encoding: [0x0f,0x01,0xc8]
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; X64-NEXT: retq ## encoding: [0xc3]
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tail call void @llvm.x86.sse3.monitor(i8* %P, i32 %E, i32 %H)
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ret void
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}
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declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind
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define void @mwait(i32 %E, i32 %H) nounwind {
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; X86-LABEL: mwait:
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; X86: ## %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x04]
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08]
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; X86-NEXT: mwait ## encoding: [0x0f,0x01,0xc9]
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; X86-NEXT: retl ## encoding: [0xc3]
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;
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; X64-LABEL: mwait:
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; X64: ## %bb.0:
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; X64-NEXT: movl %esi, %eax ## encoding: [0x89,0xf0]
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; X64-NEXT: movl %edi, %ecx ## encoding: [0x89,0xf9]
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; X64-NEXT: mwait ## encoding: [0x0f,0x01,0xc9]
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; X64-NEXT: retq ## encoding: [0xc3]
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tail call void @llvm.x86.sse3.mwait(i32 %E, i32 %H)
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ret void
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}
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declare void @llvm.x86.sse3.mwait(i32, i32) nounwind
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