forked from OSchip/llvm-project
336 lines
12 KiB
LLVM
336 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx,slow-unaligned-mem-32 | FileCheck %s
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; RUN: llc -O0 < %s -mtriple=x86_64-unknown-unknown -mattr=avx,slow-unaligned-mem-32 | FileCheck %s -check-prefix=CHECK_O0
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define void @test_256_load(double* nocapture %d, float* nocapture %f, <4 x i64>* nocapture %i) nounwind {
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; CHECK-LABEL: test_256_load:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: subq $96, %rsp
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; CHECK-NEXT: movq %rdx, %r14
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; CHECK-NEXT: movq %rsi, %r15
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; CHECK-NEXT: movq %rdi, %rbx
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; CHECK-NEXT: vmovaps (%rdi), %ymm0
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; CHECK-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
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; CHECK-NEXT: vmovaps (%rsi), %ymm1
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; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
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; CHECK-NEXT: vmovaps (%rdx), %ymm2
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; CHECK-NEXT: vmovups %ymm2, (%rsp) # 32-byte Spill
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; CHECK-NEXT: callq dummy
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; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
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; CHECK-NEXT: vmovaps %ymm0, (%rbx)
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; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
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; CHECK-NEXT: vmovaps %ymm0, (%r15)
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; CHECK-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
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; CHECK-NEXT: vmovaps %ymm0, (%r14)
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; CHECK-NEXT: addq $96, %rsp
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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;
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; CHECK_O0-LABEL: test_256_load:
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; CHECK_O0: # %bb.0: # %entry
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; CHECK_O0-NEXT: subq $152, %rsp
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; CHECK_O0-NEXT: vmovapd (%rdi), %ymm0
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; CHECK_O0-NEXT: vmovaps (%rsi), %ymm1
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; CHECK_O0-NEXT: vmovdqa (%rdx), %ymm2
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; CHECK_O0-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
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; CHECK_O0-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
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; CHECK_O0-NEXT: vmovups %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
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; CHECK_O0-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK_O0-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK_O0-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK_O0-NEXT: callq dummy
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; CHECK_O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
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; CHECK_O0-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
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; CHECK_O0-NEXT: vmovapd %ymm0, (%rax)
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; CHECK_O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
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; CHECK_O0-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload
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; CHECK_O0-NEXT: vmovaps %ymm1, (%rcx)
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; CHECK_O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
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; CHECK_O0-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload
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; CHECK_O0-NEXT: vmovdqa %ymm2, (%rdx)
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; CHECK_O0-NEXT: addq $152, %rsp
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; CHECK_O0-NEXT: vzeroupper
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; CHECK_O0-NEXT: retq
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entry:
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%0 = bitcast double* %d to <4 x double>*
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%tmp1.i = load <4 x double>, <4 x double>* %0, align 32
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%1 = bitcast float* %f to <8 x float>*
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%tmp1.i17 = load <8 x float>, <8 x float>* %1, align 32
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%tmp1.i16 = load <4 x i64>, <4 x i64>* %i, align 32
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tail call void @dummy(<4 x double> %tmp1.i, <8 x float> %tmp1.i17, <4 x i64> %tmp1.i16) nounwind
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store <4 x double> %tmp1.i, <4 x double>* %0, align 32
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store <8 x float> %tmp1.i17, <8 x float>* %1, align 32
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store <4 x i64> %tmp1.i16, <4 x i64>* %i, align 32
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ret void
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}
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declare void @dummy(<4 x double>, <8 x float>, <4 x i64>)
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;;
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;; The two tests below check that we must fold load + scalar_to_vector
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;; + ins_subvec+ zext into only a single vmovss or vmovsd or vinsertps from memory
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define <8 x float> @mov00(<8 x float> %v, float * %ptr) nounwind {
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; CHECK-LABEL: mov00:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; CHECK-NEXT: retq
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;
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; CHECK_O0-LABEL: mov00:
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; CHECK_O0: # %bb.0:
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; CHECK_O0-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; CHECK_O0-NEXT: # kill: def $ymm0 killed $xmm0
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; CHECK_O0-NEXT: retq
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%val = load float, float* %ptr
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%i0 = insertelement <8 x float> zeroinitializer, float %val, i32 0
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ret <8 x float> %i0
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}
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define <4 x double> @mov01(<4 x double> %v, double * %ptr) nounwind {
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; CHECK-LABEL: mov01:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; CHECK-NEXT: retq
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;
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; CHECK_O0-LABEL: mov01:
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; CHECK_O0: # %bb.0:
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; CHECK_O0-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; CHECK_O0-NEXT: # kill: def $ymm0 killed $xmm0
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; CHECK_O0-NEXT: retq
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%val = load double, double* %ptr
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%i0 = insertelement <4 x double> zeroinitializer, double %val, i32 0
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ret <4 x double> %i0
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}
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define void @storev16i16(<16 x i16> %a) nounwind {
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; CHECK-LABEL: storev16i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovaps %ymm0, (%rax)
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;
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; CHECK_O0-LABEL: storev16i16:
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; CHECK_O0: # %bb.0:
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; CHECK_O0-NEXT: # implicit-def: $rax
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; CHECK_O0-NEXT: vmovdqa %ymm0, (%rax)
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store <16 x i16> %a, <16 x i16>* undef, align 32
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unreachable
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}
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define void @storev16i16_01(<16 x i16> %a) nounwind {
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; CHECK-LABEL: storev16i16_01:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vextractf128 $1, %ymm0, (%rax)
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; CHECK-NEXT: vmovups %xmm0, (%rax)
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;
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; CHECK_O0-LABEL: storev16i16_01:
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; CHECK_O0: # %bb.0:
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; CHECK_O0-NEXT: # implicit-def: $rax
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; CHECK_O0-NEXT: vmovdqu %ymm0, (%rax)
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store <16 x i16> %a, <16 x i16>* undef, align 4
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unreachable
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}
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define void @storev32i8(<32 x i8> %a) nounwind {
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; CHECK-LABEL: storev32i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovaps %ymm0, (%rax)
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;
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; CHECK_O0-LABEL: storev32i8:
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; CHECK_O0: # %bb.0:
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; CHECK_O0-NEXT: # implicit-def: $rax
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; CHECK_O0-NEXT: vmovdqa %ymm0, (%rax)
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store <32 x i8> %a, <32 x i8>* undef, align 32
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unreachable
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}
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define void @storev32i8_01(<32 x i8> %a) nounwind {
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; CHECK-LABEL: storev32i8_01:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vextractf128 $1, %ymm0, (%rax)
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; CHECK-NEXT: vmovups %xmm0, (%rax)
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;
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; CHECK_O0-LABEL: storev32i8_01:
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; CHECK_O0: # %bb.0:
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; CHECK_O0-NEXT: # implicit-def: $rax
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; CHECK_O0-NEXT: vmovdqu %ymm0, (%rax)
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store <32 x i8> %a, <32 x i8>* undef, align 4
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unreachable
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}
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; It is faster to make two saves, if the data is already in xmm registers. For
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; example, after making an integer operation.
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define void @double_save(<4 x i32> %A, <4 x i32> %B, <8 x i32>* %P) nounwind ssp {
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; CHECK-LABEL: double_save:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovaps %xmm1, 16(%rdi)
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; CHECK-NEXT: vmovaps %xmm0, (%rdi)
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; CHECK-NEXT: retq
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;
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; CHECK_O0-LABEL: double_save:
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; CHECK_O0: # %bb.0:
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; CHECK_O0-NEXT: # implicit-def: $ymm2
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; CHECK_O0-NEXT: vmovaps %xmm0, %xmm2
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; CHECK_O0-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm2
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; CHECK_O0-NEXT: vmovdqu %ymm2, (%rdi)
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; CHECK_O0-NEXT: vzeroupper
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; CHECK_O0-NEXT: retq
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%Z = shufflevector <4 x i32>%A, <4 x i32>%B, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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store <8 x i32> %Z, <8 x i32>* %P, align 16
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ret void
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}
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define void @double_save_volatile(<4 x i32> %A, <4 x i32> %B, <8 x i32>* %P) nounwind {
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; CHECK-LABEL: double_save_volatile:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
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; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; CHECK-NEXT: vmovups %ymm0, (%rdi)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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;
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; CHECK_O0-LABEL: double_save_volatile:
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; CHECK_O0: # %bb.0:
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; CHECK_O0-NEXT: # implicit-def: $ymm2
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; CHECK_O0-NEXT: vmovaps %xmm0, %xmm2
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; CHECK_O0-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm2
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; CHECK_O0-NEXT: vmovdqu %ymm2, (%rdi)
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; CHECK_O0-NEXT: vzeroupper
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; CHECK_O0-NEXT: retq
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%Z = shufflevector <4 x i32>%A, <4 x i32>%B, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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store volatile <8 x i32> %Z, <8 x i32>* %P, align 16
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ret void
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}
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declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x i32>, <8 x float>) nounwind
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define void @f_f() nounwind {
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; CHECK-LABEL: f_f:
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; CHECK: # %bb.0: # %allocas
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: jne .LBB9_2
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; CHECK-NEXT: # %bb.1: # %cif_mask_all
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; CHECK-NEXT: .LBB9_2: # %cif_mask_mixed
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: jne .LBB9_4
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; CHECK-NEXT: # %bb.3: # %cif_mixed_test_all
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: vmovd %eax, %xmm0
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; CHECK-NEXT: vmaskmovps %ymm0, %ymm0, (%rax)
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; CHECK-NEXT: .LBB9_4: # %cif_mixed_test_any_check
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;
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; CHECK_O0-LABEL: f_f:
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; CHECK_O0: # %bb.0: # %allocas
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; CHECK_O0-NEXT: # implicit-def: $al
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; CHECK_O0-NEXT: testb $1, %al
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; CHECK_O0-NEXT: jne .LBB9_1
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; CHECK_O0-NEXT: jmp .LBB9_2
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; CHECK_O0-NEXT: .LBB9_1: # %cif_mask_all
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; CHECK_O0-NEXT: .LBB9_2: # %cif_mask_mixed
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; CHECK_O0-NEXT: # implicit-def: $al
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; CHECK_O0-NEXT: testb $1, %al
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; CHECK_O0-NEXT: jne .LBB9_3
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; CHECK_O0-NEXT: jmp .LBB9_4
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; CHECK_O0-NEXT: .LBB9_3: # %cif_mixed_test_all
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; CHECK_O0-NEXT: movl $-1, %eax
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; CHECK_O0-NEXT: vmovd %eax, %xmm0
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; CHECK_O0-NEXT: vmovdqa %xmm0, %xmm0
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; CHECK_O0-NEXT: vmovaps %xmm0, %xmm1
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; CHECK_O0-NEXT: # implicit-def: $rcx
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; CHECK_O0-NEXT: # implicit-def: $ymm2
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; CHECK_O0-NEXT: vmaskmovps %ymm2, %ymm1, (%rcx)
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; CHECK_O0-NEXT: .LBB9_4: # %cif_mixed_test_any_check
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allocas:
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br i1 undef, label %cif_mask_all, label %cif_mask_mixed
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cif_mask_all:
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unreachable
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cif_mask_mixed:
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br i1 undef, label %cif_mixed_test_all, label %cif_mixed_test_any_check
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cif_mixed_test_all:
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call void @llvm.x86.avx.maskstore.ps.256(i8* undef, <8 x i32> <i32 -1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, <8 x float> undef) nounwind
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unreachable
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cif_mixed_test_any_check:
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unreachable
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}
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define void @add8i32(<8 x i32>* %ret, <8 x i32>* %bp) nounwind {
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; CHECK-LABEL: add8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovups (%rsi), %xmm0
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; CHECK-NEXT: vmovups 16(%rsi), %xmm1
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; CHECK-NEXT: vmovups %xmm1, 16(%rdi)
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; CHECK-NEXT: vmovups %xmm0, (%rdi)
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; CHECK-NEXT: retq
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;
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; CHECK_O0-LABEL: add8i32:
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; CHECK_O0: # %bb.0:
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; CHECK_O0-NEXT: vmovdqu (%rsi), %xmm0
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; CHECK_O0-NEXT: vmovdqu 16(%rsi), %xmm1
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; CHECK_O0-NEXT: # implicit-def: $ymm2
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; CHECK_O0-NEXT: vmovaps %xmm0, %xmm2
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; CHECK_O0-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm2
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; CHECK_O0-NEXT: vmovdqu %ymm2, (%rdi)
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; CHECK_O0-NEXT: vzeroupper
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; CHECK_O0-NEXT: retq
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%b = load <8 x i32>, <8 x i32>* %bp, align 1
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%x = add <8 x i32> zeroinitializer, %b
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store <8 x i32> %x, <8 x i32>* %ret, align 1
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ret void
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}
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define void @add4i64a64(<4 x i64>* %ret, <4 x i64>* %bp) nounwind {
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; CHECK-LABEL: add4i64a64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovaps (%rsi), %ymm0
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; CHECK-NEXT: vmovaps %ymm0, (%rdi)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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;
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; CHECK_O0-LABEL: add4i64a64:
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; CHECK_O0: # %bb.0:
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; CHECK_O0-NEXT: vmovaps (%rsi), %ymm0
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; CHECK_O0-NEXT: vmovdqa %ymm0, (%rdi)
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; CHECK_O0-NEXT: vzeroupper
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; CHECK_O0-NEXT: retq
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%b = load <4 x i64>, <4 x i64>* %bp, align 64
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%x = add <4 x i64> zeroinitializer, %b
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store <4 x i64> %x, <4 x i64>* %ret, align 64
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ret void
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}
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define void @add4i64a16(<4 x i64>* %ret, <4 x i64>* %bp) nounwind {
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; CHECK-LABEL: add4i64a16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovaps (%rsi), %xmm0
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; CHECK-NEXT: vmovaps 16(%rsi), %xmm1
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; CHECK-NEXT: vmovaps %xmm1, 16(%rdi)
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; CHECK-NEXT: vmovaps %xmm0, (%rdi)
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; CHECK-NEXT: retq
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;
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; CHECK_O0-LABEL: add4i64a16:
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; CHECK_O0: # %bb.0:
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; CHECK_O0-NEXT: vmovdqa (%rsi), %xmm0
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; CHECK_O0-NEXT: vmovdqa 16(%rsi), %xmm1
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; CHECK_O0-NEXT: # implicit-def: $ymm2
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; CHECK_O0-NEXT: vmovaps %xmm0, %xmm2
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; CHECK_O0-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm2
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; CHECK_O0-NEXT: vmovdqu %ymm2, (%rdi)
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; CHECK_O0-NEXT: vzeroupper
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; CHECK_O0-NEXT: retq
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%b = load <4 x i64>, <4 x i64>* %bp, align 16
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%x = add <4 x i64> zeroinitializer, %b
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store <4 x i64> %x, <4 x i64>* %ret, align 16
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ret void
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}
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