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GC
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[lit] Delete empty lines at the end of lit.local.cfg NFC
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2019-06-17 09:51:07 +00:00 |
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GlobalISel
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[AArch64][GlobalISel] Make s8 and s16 G_CONSTANTs legal.
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2019-06-21 16:43:50 +00:00 |
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avx512-shuffles
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[X86][AVX] Combine vpermi(bitcast(x)) -> bitcast(vpermi(x))
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2019-07-03 14:34:16 +00:00 |
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3addr-16bit.ll
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3addr-or.ll
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Revert r356996 "[DAG] Avoid smart constructor-based dangling nodes."
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2019-03-27 19:54:41 +00:00 |
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3dnow-intrinsics.ll
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4char-promote.ll
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8bit_cmov_of_trunc_promotion.ll
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[X86] Promote i8 CMOV's (PR40965)
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2019-03-15 21:17:53 +00:00 |
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2003-08-03-CallArgLiveRanges.ll
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2003-08-23-DeadBlockTest.ll
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2003-11-03-GlobalBool.ll
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2004-02-13-FrameReturnAddress.ll
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2004-02-14-InefficientStackPointer.ll
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2004-02-22-Casts.ll
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2004-03-30-Select-Max.ll
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2004-04-13-FPCMOV-Crash.ll
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2004-06-10-StackifierCrash.ll
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2004-10-08-SelectSetCCFold.ll
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2005-01-17-CycleInDAG.ll
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2005-02-14-IllegalAssembler.ll
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2005-05-08-FPStackifierPHI.ll
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2006-01-19-ISelFoldingBug.ll
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2006-03-01-InstrSchedBug.ll
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2006-03-02-InstrSchedBug.ll
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2006-04-04-CrossBlockCrash.ll
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2006-04-27-ISelFoldingBug.ll
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2006-05-01-SchedCausingSpills.ll
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2006-05-02-InstrSched1.ll
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2006-05-02-InstrSched2.ll
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2006-05-08-CoalesceSubRegClass.ll
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2006-05-08-InstrSched.ll
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2006-05-11-InstrSched.ll
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2006-05-17-VectorArg.ll
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2006-05-22-FPSetEQ.ll
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2006-05-25-CycleInDAG.ll
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2006-07-10-InlineAsmAConstraint.ll
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2006-07-12-InlineAsmQConstraint.ll
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2006-07-20-InlineAsm.ll
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2006-07-28-AsmPrint-Long-As-Pointer.ll
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2006-07-31-SingleRegClass.ll
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2006-08-07-CycleInDAG.ll
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2006-08-16-CycleInDAG.ll
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2006-08-21-ExtraMovInst.ll
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2006-09-01-CycleInDAG.ll
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2006-10-02-BoolRetCrash.ll
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2006-10-09-CycleInDAG.ll
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2006-10-10-FindModifiedNodeSlotBug.ll
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2006-10-12-CycleInDAG.ll
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2006-10-13-CycleInDAG.ll
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2006-10-19-SwitchUnnecessaryBranching.ll
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2006-11-12-CSRetCC.ll
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2006-11-17-IllegalMove.ll
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[SelectionDAG] Add icmp UNDEF handling to SelectionDAG::FoldSetCC
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2019-03-25 18:51:57 +00:00 |
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2006-11-27-SelectLegalize.ll
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2006-12-16-InlineAsmCrash.ll
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2006-12-19-IntelSyntax.ll
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2007-01-08-InstrSched.ll
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2007-01-08-X86-64-Pointer.ll
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2007-01-13-StackPtrIndex.ll
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2007-01-29-InlineAsm-ir.ll
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2007-02-04-OrAddrMode.ll
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2007-02-16-BranchFold.ll
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2007-02-19-LiveIntervalAssert.ll
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2007-02-23-DAGCombine-Miscompile.ll
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2007-02-25-FastCCStack.ll
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2007-03-01-SpillerCrash.ll
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2007-03-15-GEP-Idx-Sink.ll
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2007-03-16-InlineAsm.ll
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2007-03-18-LiveIntervalAssert.ll
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2007-03-24-InlineAsmMultiRegConstraint.ll
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2007-03-24-InlineAsmPModifier.ll
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2007-03-24-InlineAsmVectorOp.ll
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2007-03-24-InlineAsmXConstraint.ll
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2007-03-26-CoalescerBug.ll
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2007-04-08-InlineAsmCrash.ll
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2007-04-11-InlineAsmVectorResult.ll
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2007-04-17-LiveIntervalAssert.ll
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2007-04-24-Huge-Stack.ll
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2007-04-24-VectorCrash.ll
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2007-04-27-InlineAsm-IntMemInput.ll
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2007-05-05-Personality.ll
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2007-05-05-VecCastExpand.ll
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2007-05-14-LiveIntervalAssert.ll
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2007-05-15-maskmovq.ll
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2007-05-17-ShuffleISelBug.ll
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2007-06-04-X86-64-CtorAsmBugs.ll
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[IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format
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2019-05-15 02:35:32 +00:00 |
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2007-06-28-X86-64-isel.ll
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2007-06-29-DAGCombinerBug.ll
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2007-06-29-VecFPConstantCSEBug.ll
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2007-07-03-GR64ToVR64.ll
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2007-07-10-StackerAssert.ll
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2007-07-18-Vector-Extract.ll
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2007-08-01-LiveVariablesBug.ll
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2007-08-09-IllegalX86-64Asm.ll
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2007-08-10-SignExtSubreg.ll
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2007-09-05-InvalidAsm.ll
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2007-09-06-ExtWeakAliasee.ll
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2007-09-27-LDIntrinsics.ll
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2007-10-04-AvoidEFLAGSCopy.ll
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2007-10-12-CoalesceExtSubReg.ll
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2007-10-12-SpillerUnfold1.ll
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2007-10-12-SpillerUnfold2.ll
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2007-10-14-CoalescerCrash.ll
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2007-10-15-CoalescerCrash.ll
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2007-10-16-CoalescerCrash.ll
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2007-10-19-SpillerUnfold.ll
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2007-10-28-inlineasm-q-modifier.ll
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2007-10-29-ExtendSetCC.ll
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2007-10-30-LSRCrash.ll
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2007-10-31-extractelement-i64.ll
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2007-11-01-ISelCrash.ll
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2007-11-03-x86-64-q-constraint.ll
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2007-11-04-LiveIntervalCrash.ll
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2007-11-04-LiveVariablesBug.ll
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2007-11-04-rip-immediate-constant.ll
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2007-11-06-InstrSched.ll
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2007-11-07-MulBy4.ll
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2007-11-30-LoadFolding-Bug.ll
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2007-12-16-BURRSchedCrash.ll
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2007-12-18-LoadCSEBug.ll
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2008-01-08-IllegalCMP.ll
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2008-01-08-SchedulerCrash.ll
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2008-01-09-LongDoubleSin.ll
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2008-01-16-FPStackifierAssert.ll
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2008-01-16-InvalidDAGCombineXform.ll
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2008-02-05-ISelCrash.ll
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2008-02-06-LoadFoldingBug.ll
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2008-02-14-BitMiscompile.ll
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2008-02-18-TailMergingBug.ll
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2008-02-20-InlineAsmClobber.ll
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2008-02-22-LocalRegAllocBug.ll
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2008-02-25-InlineAsmBug.ll
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2008-02-25-X86-64-CoalescerBug.ll
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2008-02-26-AsmDirectMemOp.ll
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2008-02-27-DeadSlotElimBug.ll
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2008-02-27-PEICrash.ll
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2008-03-06-frem-fpstack.ll
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2008-03-07-APIntBug.ll
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2008-03-10-RegAllocInfLoop.ll
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2008-03-12-ThreadLocalAlias.ll
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2008-03-13-TwoAddrPassCrash.ll
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2008-03-14-SpillerCrash.ll
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2008-03-19-DAGCombinerBug.ll
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2008-03-23-DarwinAsmComments.ll
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2008-03-25-TwoAddrPassBug.ll
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2008-03-31-SpillerFoldingBug.ll
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2008-04-02-unnamedEH.ll
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2008-04-08-CoalescerCrash.ll
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2008-04-09-BranchFolding.ll
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2008-04-15-LiveVariableBug.ll
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2008-04-16-CoalescerBug.ll
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2008-04-16-ReMatBug.ll
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2008-04-17-CoalescerBug.ll
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2008-04-24-MemCpyBug.ll
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2008-04-24-pblendw-fold-crash.ll
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2008-04-26-Asm-Optimize-Imm.ll
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2008-04-28-CoalescerBug.ll
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2008-04-28-CyclicSchedUnit.ll
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2008-05-01-InvalidOrdCompare.ll
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2008-05-09-PHIElimBug.ll
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2008-05-09-ShuffleLoweringBug.ll
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2008-05-12-tailmerge-5.ll
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2008-05-21-CoalescerBug.ll
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2008-05-22-FoldUnalignedLoad.ll
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2008-05-28-CoalescerBug.ll
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2008-05-28-LocalRegAllocBug.ll
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2008-06-13-NotVolatileLoadStore.ll
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2008-06-13-VolatileLoadStore.ll
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2008-06-16-SubregsBug.ll
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2008-06-25-VecISelBug.ll
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2008-07-07-DanglingDeadInsts.ll
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2008-07-09-ELFSectionAttributes.ll
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2008-07-11-SHLBy1.ll
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2008-07-16-CoalescerCrash.ll
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2008-07-19-movups-spills.ll
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2008-07-22-CombinerCrash.ll
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2008-07-23-VSetCC.ll
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2008-08-06-CmpStride.ll
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2008-08-06-RewriterBug.ll
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2008-08-17-UComiCodeGenBug.ll
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2008-08-23-64Bit-maskmovq.ll
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2008-08-31-EH_RETURN32.ll
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2008-08-31-EH_RETURN64.ll
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2008-09-05-sinttofp-2xi32.ll
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2008-09-09-LinearScanBug.ll
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2008-09-11-CoalescerBug.ll
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2008-09-11-CoalescerBug2.ll
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2008-09-17-inline-asm-1.ll
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2008-09-18-inline-asm-2.ll
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2008-09-19-RegAllocBug.ll
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2008-09-25-sseregparm-1.ll
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2008-09-26-FrameAddrBug.ll
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2008-09-29-ReMatBug.ll
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2008-09-29-VolatileBug.ll
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[X86] Prevent folding a load into an AND if that AND is really a ZEXT_INREG that should use movzx.
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2019-04-24 19:28:38 +00:00 |
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2008-10-06-x87ld-nan-1.ll
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2008-10-06-x87ld-nan-2.ll
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2008-10-07-SSEISelBug.ll
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2008-10-11-CallCrash.ll
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2008-10-13-CoalescerBug.ll
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2008-10-16-VecUnaryOp.ll
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2008-10-17-Asm64bitRConstraint.ll
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2008-10-20-AsmDoubleInI32.ll
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2008-10-24-FlippedCompare.ll
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2008-10-27-CoalescerBug.ll
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2008-10-29-ExpandVAARG.ll
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2008-11-03-F80VAARG.ll
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2008-11-06-testb.ll
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2008-11-13-inlineasm-3.ll
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2008-11-29-ULT-Sign.ll
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2008-12-01-SpillerAssert.ll
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2008-12-01-loop-iv-used-outside-loop.ll
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2008-12-02-IllegalResultType.ll
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2008-12-02-dagcombine-1.ll
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2008-12-02-dagcombine-2.ll
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2008-12-02-dagcombine-3.ll
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2008-12-16-dagcombine-4.ll
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2008-12-19-EarlyClobberBug.ll
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2008-12-22-dagcombine-5.ll
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2008-12-23-crazy-address.ll
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2008-12-23-dagcombine-6.ll
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2009-01-13-DoubleUpdate.ll
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2009-01-16-SchedulerBug.ll
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2009-01-16-UIntToFP.ll
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2009-01-18-ConstantExprCrash.ll
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2009-01-25-NoSSE.ll
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2009-01-26-WrongCheck.ll
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2009-01-27-NullStrings.ll
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2009-01-31-BigShift.ll
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2009-01-31-BigShift2.ll
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2009-01-31-BigShift3.ll
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2009-02-01-LargeMask.ll
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2009-02-03-AnalyzedTwice.ll
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2009-02-04-sext-i64-gep.ll
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2009-02-08-CoalescerBug.ll
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2009-02-09-ivs-different-sizes.ll
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2009-02-11-codegenprepare-reuse.ll
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2009-02-12-DebugInfoVLA.ll
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2009-02-12-InlineAsm-nieZ-constraints.ll
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2009-02-12-SpillerBug.ll
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2009-02-21-ExtWeakInitializer.ll
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2009-02-25-CommuteBug.ll
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2009-02-26-MachineLICMBug.ll
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[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
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2019-05-06 21:39:51 +00:00 |
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2009-03-03-BTHang.ll
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2009-03-03-BitcastLongDouble.ll
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2009-03-05-burr-list-crash.ll
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2009-03-09-APIntCrash.ll
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2009-03-09-SpillerBug.ll
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2009-03-10-CoalescerBug.ll
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2009-03-12-CPAlignBug.ll
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2009-03-13-PHIElimBug.ll
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2009-03-16-PHIElimInLPad.ll
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2009-03-23-LinearScanBug.ll
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2009-03-23-MultiUseSched.ll
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2009-03-23-i80-fp80.ll
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2009-03-25-TestBug.ll
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2009-03-26-NoImplicitFPBug.ll
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2009-04-12-FastIselOverflowCrash.ll
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2009-04-12-picrel.ll
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2009-04-13-2AddrAssert-2.ll
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2009-04-13-2AddrAssert.ll
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2009-04-14-IllegalRegs.ll
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2009-04-16-SpillerUnfold.ll
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2009-04-24.ll
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2009-04-25-CoalescerBug.ll
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2009-04-27-CoalescerAssert.ll
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2009-04-27-LiveIntervalsAssert.ll
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2009-04-27-LiveIntervalsAssert2.ll
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2009-04-29-IndirectDestOperands.ll
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2009-04-29-LinearScanBug.ll
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2009-04-29-RegAllocAssert.ll
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2009-04-scale.ll
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2009-05-08-InlineAsmIOffset.ll
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2009-05-11-tailmerge-crash.ll
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2009-05-19-SingleElementExtractElement.ll
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2009-05-23-available_externally.ll
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2009-05-23-dagcombine-shifts.ll
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2009-05-28-DAGCombineCrash.ll
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2009-05-30-ISelBug.ll
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2009-06-02-RewriterBug.ll
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2009-06-03-Win64DisableRedZone.ll
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2009-06-03-Win64SpillXMM.ll
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2009-06-04-VirtualLiveIn.ll
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2009-06-05-VZextByteShort.ll
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2009-06-05-VariableIndexInsert.ll
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2009-06-05-sitofpCrash.ll
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2009-06-06-ConcatVectors.ll
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2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll
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2009-06-15-not-a-tail-call.ll
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2009-06-18-movlp-shuffle-register.ll
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2009-07-06-TwoAddrAssert.ll
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2009-07-07-SplitICmp.ll
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2009-07-09-ExtractBoolFromVector.ll
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2009-07-15-CoalescerBug.ll
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2009-07-16-CoalescerBug.ll
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2009-07-19-AsmExtraOperands.ll
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2009-07-20-CoalescerBug.ll
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2009-07-20-DAGCombineBug.ll
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2009-08-06-branchfolder-crash.ll
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2009-08-06-inlineasm.ll
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2009-08-08-CastError.ll
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2009-08-12-badswitch.ll
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2009-08-14-Win64MemoryIndirectArg.ll
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2009-08-19-LoadNarrowingMiscompile.ll
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2009-08-23-SubRegReuseUndo.ll
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2009-09-10-LoadFoldingBug.ll
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2009-09-10-SpillComments.ll
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2009-09-16-CoalescerBug.ll
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2009-09-19-earlyclobber.ll
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2009-09-21-NoSpillLoopCount.ll
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2009-09-22-CoalescerBug.ll
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2009-09-23-LiveVariablesBug.ll
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2009-10-14-LiveVariablesBug.ll
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2009-10-16-Scope.ll
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2009-10-19-EmergencySpill.ll
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2009-10-19-atomic-cmp-eflags.ll
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2009-10-25-RewriterBug.ll
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2009-11-04-SubregCoalescingBug.ll
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2009-11-13-VirtRegRewriterBug.ll
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2009-11-16-MachineLICM.ll
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2009-11-16-UnfoldMemOpBug.ll
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2009-11-17-UpdateTerminator.ll
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2009-11-18-TwoAddrKill.ll
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2009-11-25-ImpDefBug.ll
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2009-12-01-EarlyClobberBug.ll
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2009-12-11-TLSNoRedZone.ll
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2010-01-05-ZExt-Shl.ll
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2010-01-07-ISelBug.ll
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2010-01-08-Atomic64Bug.ll
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2010-01-11-ExtraPHIArg.ll
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2010-01-13-OptExtBug.ll
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2010-01-15-SelectionDAGCycle.ll
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2010-01-18-DbgValue.ll
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2010-01-19-OptExtBug.ll
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2010-02-01-DbgValueCrash.ll
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2010-02-01-TaillCallCrash.ll
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2010-02-03-DualUndef.ll
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2010-02-04-SchedulerBug.ll
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2010-02-11-NonTemporal.ll
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2010-02-12-CoalescerBug-Impdef.ll
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2010-02-15-ImplicitDefBug.ll
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2010-02-19-TailCallRetAddrBug.ll
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2010-02-23-DAGCombineBug.ll
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[X86] Avoid icmp undef in reduced tests
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2019-03-13 18:36:59 +00:00 |
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2010-02-23-DIV8rDefinesAX.ll
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2010-02-23-RematImplicitSubreg.ll
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2010-02-23-SingleDefPhiJoin.ll
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2010-03-04-Mul8Bug.ll
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2010-03-05-ConstantFoldCFG.ll
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2010-03-05-EFLAGS-Redef.ll
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2010-03-17-ISelBug.ll
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2010-04-06-SSEDomainFixCrash.ll
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2010-04-08-CoalescerBug.ll
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2010-04-13-AnalyzeBranchCrash.ll
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2010-04-21-CoalescerBug.ll
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2010-04-29-CoalescerCrash.ll
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2010-04-30-LocalAlloc-LandingPad.ll
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2010-05-03-CoalescerSubRegClobber.ll
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2010-05-05-LocalAllocEarlyClobber.ll
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2010-05-06-LocalInlineAsmClobber.ll
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2010-05-07-ldconvert.ll
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2010-05-10-DAGCombinerBug.ll
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2010-05-12-FastAllocKills.ll
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2010-05-16-nosseconversion.ll
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2010-05-25-DotDebugLoc.ll
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2010-05-26-DotDebugLoc.ll
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2010-05-26-FP_TO_INT-crash.ll
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2010-05-28-Crash.ll
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2010-06-01-DeadArg-DbgInfo.ll
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2010-06-09-FastAllocRegisters.ll
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2010-06-14-fast-isel-fs-load.ll
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2010-06-15-FastAllocEarlyCLobber.ll
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2010-06-24-g-constraint-crash.ll
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2010-06-25-CoalescerSubRegDefDead.ll
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2010-06-25-asm-RA-crash.ll
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2010-06-28-FastAllocTiedOperand.ll
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2010-06-28-matched-g-constraint.ll
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2010-07-02-UnfoldBug.ll
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2010-07-02-asm-alignstack.ll
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2010-07-06-DbgCrash.ll
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2010-07-06-asm-RIP.ll
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2010-07-11-FPStackLoneUse.ll
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2010-07-13-indirectXconstraint.ll
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2010-07-15-Crash.ll
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2010-07-29-SetccSimplify.ll
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2010-08-04-MaskedSignedCompare.ll
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[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
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2019-06-13 13:56:19 +00:00 |
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2010-08-04-MingWCrash.ll
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2010-08-04-StackVariable.ll
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2010-09-01-RemoveCopyByCommutingDef.ll
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2010-09-16-EmptyFilename.ll
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2010-09-16-asmcrash.ll
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2010-09-17-SideEffectsInChain.ll
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2010-09-30-CMOV-JumpTable-PHI.ll
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2010-10-08-cmpxchg8b.ll
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2010-11-02-DbgParameter.ll
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2010-11-09-MOVLPS.ll
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2010-11-18-SelectOfExtload.ll
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2011-01-07-LegalizeTypesCrash.ll
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2011-01-10-DagCombineHang.ll
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2011-01-24-DbgValue-Before-Use.ll
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2011-02-04-FastRegallocNoFP.ll
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2011-02-12-shuffle.ll
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2011-02-21-VirtRegRewriter-KillSubReg.ll
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2011-02-23-UnfoldBug.ll
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2011-02-27-Fpextend.ll
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2011-03-02-DAGCombiner.ll
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2011-03-08-Sched-crash.ll
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2011-03-09-Physreg-Coalescing.ll
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2011-03-30-CreateFixedObjCrash.ll
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2011-04-13-SchedCmpJmp.ll
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2011-04-19-sclr-bb.ll
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2011-05-09-loaduse.ll
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2011-05-26-UnreachableBlockElim.ll
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2011-05-27-CrossClassCoalescing.ll
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2011-06-01-fildll.ll
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2011-06-03-x87chain.ll
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2011-06-06-fgetsign80bit.ll
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2011-06-12-FastAllocSpill.ll
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2011-06-14-PreschedRegalias.ll
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2011-06-14-mmx-inlineasm.ll
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2011-06-19-QuicksortCoalescerBug.ll
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2011-07-13-BadFrameIndexDisplacement.ll
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2011-08-23-PerformSubCombine128.ll
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2011-08-23-Trampoline.ll
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2011-08-29-BlockConstant.ll
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2011-08-29-InitOrder.ll
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[IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format
|
2019-05-15 02:35:32 +00:00 |
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2011-09-14-valcoalesce.ll
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2011-09-18-sse2cmp.ll
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2011-09-21-setcc-bug.ll
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2011-10-11-SpillDead.ll
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2011-10-11-srl.ll
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2011-10-12-MachineCSE.ll
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2011-10-18-FastISel-VectorParams.ll
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2011-10-19-LegelizeLoad.ll
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2011-10-19-widen_vselect.ll
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[X86] Fix some tests using fcmp with undef arguments
|
2019-03-29 17:20:27 +00:00 |
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2011-10-21-widen-cmp.ll
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[X86] Fix some tests using fcmp with undef arguments
|
2019-03-29 17:20:27 +00:00 |
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2011-10-27-tstore.ll
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2011-10-30-padd.ll
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2011-11-07-LegalizeBuildVector.ll
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2011-11-22-AVX2-Domains.ll
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2011-11-30-or.ll
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2011-12-06-AVXVectorExtractCombine.ll
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2011-12-06-BitcastVectorGlobal.ll
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2011-12-08-AVXISelBugs.ll
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2011-12-8-bitcastintprom.ll
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2011-12-15-vec_shift.ll
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2011-12-26-extractelement-duplicate-load.ll
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2011-12-28-vselecti8.ll
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Recommit r354647 and r354648 "[LegalizeTypes] When promoting the result of EXTRACT_SUBVECTOR, also check if the input needs to be promoted. Use that to determine the element type to extract"
|
2019-02-23 19:51:32 +00:00 |
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2011-20-21-zext-ui2fp.ll
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2012-01-10-UndefExceptionEdge.ll
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2012-1-10-buildvector.ll
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2012-01-11-split-cv.ll
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2012-01-12-extract-sv.ll
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2012-01-16-mfence-nosse-flags.ll
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2012-01-18-vbitcast.ll
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2012-02-12-dagco.ll
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2012-02-14-scalar.ll
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2012-02-23-mmx-inlineasm.ll
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2012-02-29-CoalescerBug.ll
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2012-03-15-build_vector_wl.ll
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2012-03-20-LargeConstantExpr.ll
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2012-03-26-PostRALICMBug.ll
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2012-04-09-TwoAddrPassBug.ll
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2012-04-26-sdglue.ll
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2012-05-17-TwoAddressBug.ll
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2012-05-19-CoalescerCrash.ll
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2012-07-10-extload64.ll
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[DAGCombiner] loosen restrictions for moving shuffles after vector binop
|
2019-04-03 13:42:06 +00:00 |
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2012-07-10-shufnorm.ll
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2012-07-15-BuildVectorPromote.ll
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2012-07-15-broadcastfold.ll
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2012-07-15-tconst_shl.ll
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2012-07-15-vshl.ll
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2012-07-16-LeaUndef.ll
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2012-07-16-fp2ui-i1.ll
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2012-07-17-vtrunc.ll
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2012-07-23-select_cc.ll
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2012-08-07-CmpISelBug.ll
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[X86] Regenerate CmpISel test for future patch
|
2019-06-11 15:13:11 +00:00 |
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2012-08-16-setcc.ll
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2012-08-17-legalizer-crash.ll
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2012-08-28-UnsafeMathCrash.ll
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2012-09-13-dagco-fneg.ll
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2012-09-28-CGPBug.ll
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2012-10-02-DAGCycle.ll
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2012-10-03-DAGCycle.ll
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2012-10-18-crash-dagco.ll
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2012-11-28-merge-store-alias.ll
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2012-12-1-merge-multiple.ll
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2012-12-12-DAGCombineCrash.ll
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2012-12-14-v8fp80-crash.ll
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2012-12-19-NoImplicitFloat.ll
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2013-01-09-DAGCombineBug.ll
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2013-03-13-VEX-DestReg.ll
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2013-05-06-ConactVectorCrash.ll
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2013-10-14-FastISel-incorrect-vreg.ll
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2014-05-29-factorial.ll
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2014-08-29-CompactUnwind.ll
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9601.ll
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20090313-signext.ll
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AppendingLinkage.ll
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Atomics-64.ll
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DbgValueOtherTargets.test
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…
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DynamicCalleeSavedRegisters.ll
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…
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MachineBranchProb.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
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MachineSink-CritEdge.ll
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…
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MachineSink-DbgValue.ll
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MachineSink-PHIUse.ll
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…
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MachineSink-SubReg.ll
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…
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MachineSink-eflags.ll
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[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
|
2019-06-13 13:56:19 +00:00 |
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MergeConsecutiveStores.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
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O0-pipeline.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
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O3-pipeline.ll
|
Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."
|
2019-06-26 12:13:13 +00:00 |
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PR34565.ll
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…
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PR37310.mir
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Describe stack-id as an enum
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2019-06-17 09:13:29 +00:00 |
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PR40322.ll
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[X86] Run CFIInstrInserter on Windows if Dwarf is used
|
2019-04-29 20:25:51 +00:00 |
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StackColoring-dbg.ll
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…
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StackColoring.ll
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SwitchLowering.ll
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SwizzleShuff.ll
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TruncAssertSext.ll
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TruncAssertZext.ll
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WidenArith.ll
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…
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abi-isel.ll
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…
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absolute-bit-mask-fastisel.ll
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…
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absolute-bit-mask.ll
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…
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absolute-bt.ll
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…
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absolute-cmp.ll
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…
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absolute-constant.ll
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…
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absolute-rotate.ll
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[X86] Use relocImm in the ROL8ri/ROL16ri/ROL32ri/ROL64ri patterns to be consistent with the ROR patterns.
|
2019-03-18 20:43:15 +00:00 |
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add-ext.ll
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[DAG] Refactor DAGCombiner::ReassociateOps
|
2019-04-29 17:50:10 +00:00 |
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add-i64.ll
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…
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add-of-carry.ll
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[DAGCombiner] Don't combine (addcarry (uaddo X, Y), 0, Carry) -> (addcarry X, Y, Carry) if the Carry comes from the uaddo.
|
2019-07-04 18:18:46 +00:00 |
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add-sub-nsw-nuw.ll
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…
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add.ll
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[X86] Pre commit test cases for D64574. Along with a test case for PR42571. NFC
|
2019-07-11 18:19:27 +00:00 |
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add32ri8.ll
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…
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|
add_shl_constant.ll
|
…
|
|
|
addcarry.ll
|
[DAGCombine] More diamong carry pattern optimization.
|
2019-07-03 16:15:59 +00:00 |
|
addcarry2.ll
|
…
|
|
|
addr-label-difference.ll
|
…
|
|
|
addr-mode-matcher-2.ll
|
[Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr)
|
2019-06-25 17:29:18 +00:00 |
|
addr-mode-matcher.ll
|
…
|
|
|
addr-of-ret-addr.ll
|
…
|
|
|
address-type-promotion-constantexpr.ll
|
…
|
|
|
addrsig.ll
|
…
|
|
|
addsub-constant-folding.ll
|
[NFC][Codegen] Add/sub constant-folding: add scalar tests too
|
2019-05-31 08:23:48 +00:00 |
|
adx-commute.mir
|
…
|
|
|
adx-intrinsics-upgrade.ll
|
…
|
|
|
adx-intrinsics.ll
|
…
|
|
|
aes_intrinsics.ll
|
…
|
|
|
alias-gep.ll
|
…
|
|
|
alias-static-alloca.ll
|
…
|
|
|
aliases.ll
|
…
|
|
|
aligned-comm.ll
|
…
|
|
|
aligned-variadic.ll
|
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
|
2019-03-13 17:07:09 +00:00 |
|
alignment-2.ll
|
…
|
|
|
alignment.ll
|
…
|
|
|
all-ones-vector.ll
|
…
|
|
|
alldiv-divdi3.ll
|
…
|
|
|
alloca-align-rounding-32.ll
|
…
|
|
|
alloca-align-rounding.ll
|
…
|
|
|
allrem-moddi3.ll
|
…
|
|
|
and-encoding.ll
|
…
|
|
|
and-load-fold.ll
|
…
|
|
|
and-or-fold.ll
|
…
|
|
|
and-sink.ll
|
…
|
|
|
and-su.ll
|
…
|
|
|
andimm8.ll
|
…
|
|
|
anyext.ll
|
…
|
|
|
anyregcc-crash.ll
|
RegAlloc: try to fail more gracefully when out of registers
|
2019-05-15 17:29:58 +00:00 |
|
anyregcc.ll
|
…
|
|
|
apm.ll
|
[X86] Remove CustomInserter pseudos for MONITOR/MONITORX/CLZERO. Use custom instruction selection instead.
|
2019-04-03 23:28:30 +00:00 |
|
arg-cast.ll
|
…
|
|
|
arg-copy-elide-win64.ll
|
[X86] Disable argument copy elision for arguments passed via pointers
|
2019-04-20 15:26:44 +00:00 |
|
arg-copy-elide.ll
|
…
|
|
|
arg_returned_bitcast.ll
|
[SelectionDAG][FIX] Allow "returned" arguments to be bit-casted
|
2019-06-04 20:34:43 +00:00 |
|
asm-block-labels.ll
|
…
|
|
|
asm-global-imm.ll
|
…
|
|
|
asm-indirect-mem.ll
|
…
|
|
|
asm-invalid-register-class-crasher.ll
|
…
|
|
|
asm-label.ll
|
…
|
|
|
asm-label2.ll
|
…
|
|
|
asm-mismatched-types.ll
|
…
|
|
|
asm-modifier-P.ll
|
…
|
|
|
asm-modifier.ll
|
…
|
|
|
asm-reg-type-mismatch-avx512.ll
|
[X86] Add test case that was supposed to go with r360102.
|
2019-05-24 04:46:56 +00:00 |
|
asm-reg-type-mismatch.ll
|
…
|
|
|
asm-reject-reg-type-mismatch.ll
|
…
|
|
|
asm-reject-rex.ll
|
…
|
|
|
asm-reject-vk32-vk64.ll
|
[X86] Block i32/i64 for 'k' and 'Yk' in getRegForInlineAsmConstraint without avx512bw.
|
2019-04-15 18:39:45 +00:00 |
|
asm-reject-xmm16.ll
|
…
|
|
|
atom-call-reg-indirect-foldedreload32.ll
|
…
|
|
|
atom-call-reg-indirect-foldedreload64.ll
|
…
|
|
|
atom-call-reg-indirect.ll
|
…
|
|
|
atom-cmpb.ll
|
…
|
|
|
atom-fixup-lea1.ll
|
…
|
|
|
atom-fixup-lea2.ll
|
…
|
|
|
atom-fixup-lea3.ll
|
…
|
|
|
atom-fixup-lea4.ll
|
…
|
|
|
atom-lea-addw-bug.ll
|
…
|
|
|
atom-lea-sp.ll
|
…
|
|
|
atom-pad-short-functions.ll
|
…
|
|
|
atom-sched.ll
|
…
|
|
|
atom-shuf.ll
|
…
|
|
|
atomic-add.ll
|
[Tests] Auto update a test
|
2019-02-13 17:30:03 +00:00 |
|
atomic-dagsched.ll
|
…
|
|
|
atomic-eflags-reuse.ll
|
…
|
|
|
atomic-flags.ll
|
…
|
|
|
atomic-fp.ll
|
[X86] Use MOVQ for i64 atomic_stores when SSE2 is enabled
|
2019-04-27 03:38:15 +00:00 |
|
atomic-idempotent.ll
|
Use an offset from TOS for idempotent rmw locked op lowering
|
2019-05-14 22:32:42 +00:00 |
|
atomic-load-store-wide.ll
|
[X86] Prefer locked stack op over mfence for seq_cst 64-bit stores on 32-bit targets
|
2019-05-14 04:43:37 +00:00 |
|
atomic-load-store.ll
|
…
|
|
|
atomic-mi.ll
|
Recommit r358211 "[X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87, but no SSE2"
|
2019-04-11 19:19:42 +00:00 |
|
atomic-minmax-i6432.ll
|
…
|
|
|
atomic-monotonic.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
atomic-non-integer.ll
|
[X86] Prefer locked stack op over mfence for seq_cst 64-bit stores on 32-bit targets
|
2019-05-14 04:43:37 +00:00 |
|
atomic-op.ll
|
[Tests] Rename some test files for consistency
|
2019-02-13 17:23:11 +00:00 |
|
atomic-ops-ancient-64.ll
|
…
|
|
|
atomic-or.ll
|
…
|
|
|
atomic-pointer.ll
|
IR: Support parsing numeric block ids, and emit them in textual output.
|
2019-03-22 18:27:13 +00:00 |
|
atomic-unordered.ll
|
[FastISel] Skip creating unnecessary vregs for arguments
|
2019-06-10 16:53:37 +00:00 |
|
atomic8.ll
|
…
|
|
|
atomic16.ll
|
…
|
|
|
atomic32.ll
|
Reapply r359906, "RegAllocFast: Add heuristic to detect values not live-out of a block"
|
2019-05-03 19:06:57 +00:00 |
|
atomic64.ll
|
Reapply r359906, "RegAllocFast: Add heuristic to detect values not live-out of a block"
|
2019-05-03 19:06:57 +00:00 |
|
atomic128.ll
|
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b()
|
2019-03-13 18:48:50 +00:00 |
|
atomic6432.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
atomicf128.ll
|
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b()
|
2019-03-13 18:48:50 +00:00 |
|
attribute-sections.ll
|
…
|
|
|
avg-mask.ll
|
…
|
|
|
avg.ll
|
[X86][AVX] combineExtractSubvector - 'little to big' extract_subvector(bitcast()) support
|
2019-06-26 11:21:09 +00:00 |
|
avoid-lea-scale2.ll
|
…
|
|
|
avoid-loop-align-2.ll
|
…
|
|
|
avoid-loop-align.ll
|
…
|
|
|
avoid-sfb-g-no-change.mir
|
Resubmit r360436 "[X86] Avoid SFB - Fix inconsistent codegen with/without debug info"
|
2019-05-23 18:15:12 +00:00 |
|
avoid-sfb-g-no-change2.mir
|
[X86] Avoid SFB - Fix inconsistent codegen with/without debug info(2)
|
2019-07-01 18:28:21 +00:00 |
|
avoid-sfb-g-no-change3.mir
|
[X86] Avoid SFB - Fix inconsistent codegen with/without debug info(2)
|
2019-07-01 18:28:21 +00:00 |
|
avoid-sfb-kill-flags.mir
|
…
|
|
|
avoid-sfb-offset.mir
|
Describe stack-id as an enum
|
2019-06-17 09:13:29 +00:00 |
|
avoid-sfb-overlaps.ll
|
…
|
|
|
avoid-sfb.ll
|
…
|
|
|
avoid_complex_am.ll
|
…
|
|
|
avx-arith.ll
|
…
|
|
|
avx-basic.ll
|
…
|
|
|
avx-bitcast.ll
|
…
|
|
|
avx-brcond.ll
|
…
|
|
|
avx-cast.ll
|
…
|
|
|
avx-cmp.ll
|
[X86] Fix some tests using fcmp with undef arguments
|
2019-03-29 17:20:27 +00:00 |
|
avx-cvt-2.ll
|
…
|
|
|
avx-cvt-3.ll
|
Recommit r354363 "[X86][SSE] Generalize X86ISD::BLENDI support to more value types"
|
2019-02-23 21:41:42 +00:00 |
|
avx-cvt.ll
|
…
|
|
|
avx-cvttp2si.ll
|
…
|
|
|
avx-fp2int.ll
|
…
|
|
|
avx-gfni-intrinsics.ll
|
…
|
|
|
avx-insertelt.ll
|
…
|
|
|
avx-intel-ocl.ll
|
…
|
|
|
avx-intrinsics-fast-isel.ll
|
…
|
|
|
avx-intrinsics-x86-upgrade.ll
|
[x86] split 256-bit store of concatenated vectors
|
2019-06-04 16:40:04 +00:00 |
|
avx-intrinsics-x86.ll
|
[x86] split 256-bit store of concatenated vectors
|
2019-06-04 16:40:04 +00:00 |
|
avx-intrinsics-x86_64.ll
|
…
|
|
|
avx-isa-check.ll
|
…
|
|
|
avx-load-store.ll
|
[X86] Add DAG combine to turn (vzmovl (insert_subvector undef, X, 0)) into (insert_subvector allzeros, (vzmovl X), 0)
|
2019-06-21 19:10:21 +00:00 |
|
avx-logic.ll
|
…
|
|
|
avx-minmax.ll
|
…
|
|
|
avx-select.ll
|
…
|
|
|
avx-shift.ll
|
…
|
|
|
avx-shuffle-x86_32.ll
|
…
|
|
|
avx-splat.ll
|
…
|
|
|
avx-trunc.ll
|
…
|
|
|
avx-unpack.ll
|
…
|
|
|
avx-varargs-x86_64.ll
|
…
|
|
|
avx-vbroadcast.ll
|
[X86][AVX] Add test case showing failure to fold broadcast load if its also used as a scalar
|
2019-04-02 10:31:00 +00:00 |
|
avx-vbroadcastf128.ll
|
…
|
|
|
avx-vextractf128.ll
|
…
|
|
|
avx-vinsertf128.ll
|
…
|
|
|
avx-vpclmulqdq.ll
|
…
|
|
|
avx-vperm2x128.ll
|
…
|
|
|
avx-vzeroupper.ll
|
…
|
|
|
avx-win64-args.ll
|
…
|
|
|
avx-win64.ll
|
…
|
|
|
avx.ll
|
…
|
|
|
avx1-logical-load-folding.ll
|
[x86] scalarize extract element 0 of FP math
|
2019-02-28 19:47:04 +00:00 |
|
avx2-arith.ll
|
…
|
|
|
avx2-cmp.ll
|
…
|
|
|
avx2-conversions.ll
|
[x86] split more v8f32/v8i32 shuffles in lowering
|
2019-02-18 16:46:12 +00:00 |
|
avx2-fma-fneg-combine.ll
|
…
|
|
|
avx2-gather.ll
|
…
|
|
|
avx2-intrinsics-canonical.ll
|
[X86] Regenerate tests. NFCI.
|
2019-07-10 17:22:31 +00:00 |
|
avx2-intrinsics-fast-isel.ll
|
[X86] Restore the pavg intrinsics.
|
2019-04-15 17:17:35 +00:00 |
|
avx2-intrinsics-x86-upgrade.ll
|
[X86] Restore the pavg intrinsics.
|
2019-04-15 17:17:35 +00:00 |
|
avx2-intrinsics-x86.ll
|
[X86] Restore the pavg intrinsics.
|
2019-04-15 17:17:35 +00:00 |
|
avx2-logic.ll
|
…
|
|
|
avx2-masked-gather.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
avx2-nontemporal.ll
|
…
|
|
|
avx2-phaddsub.ll
|
[X86][SSE] Fold add(shuffle(),shuffle()) to hadd on 'slow' targets (PR39920)
|
2019-05-09 17:45:01 +00:00 |
|
avx2-pmovxrm.ll
|
…
|
|
|
avx2-shift.ll
|
…
|
|
|
avx2-vbroadcast.ll
|
[X86][AVX] Only combine loads to broadcasts for legal types
|
2019-02-27 11:17:25 +00:00 |
|
avx2-vbroadcasti128.ll
|
…
|
|
|
avx2-vector-shifts.ll
|
[x86] split more v8f32/v8i32 shuffles in lowering
|
2019-02-18 16:46:12 +00:00 |
|
avx2-vperm.ll
|
…
|
|
|
avx512-adc-sbb.ll
|
…
|
|
|
avx512-any_extend_load.ll
|
…
|
|
|
avx512-arith.ll
|
…
|
|
|
avx512-bugfix-23634.ll
|
…
|
|
|
avx512-bugfix-25270.ll
|
…
|
|
|
avx512-bugfix-26264.ll
|
…
|
|
|
avx512-build-vector.ll
|
…
|
|
|
avx512-calling-conv.ll
|
…
|
|
|
avx512-cmp-kor-sequence.ll
|
…
|
|
|
avx512-cmp.ll
|
…
|
|
|
avx512-cvt-widen.ll
|
[SelectionDAG] Add [us]itofp(undef) --> 0 constant fold (PR39205)
|
2019-06-03 13:02:07 +00:00 |
|
avx512-cvt.ll
|
[X86] Fix the pattern for merge masked vcvtps2pd.
|
2019-06-03 19:29:14 +00:00 |
|
avx512-cvttp2i.ll
|
…
|
|
|
avx512-ext.ll
|
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
|
2019-06-25 10:51:15 +00:00 |
|
avx512-extract-subvector-load-store.ll
|
…
|
|
|
avx512-extract-subvector.ll
|
…
|
|
|
avx512-fma-commute.ll
|
…
|
|
|
avx512-fma-intrinsics-upgrade.ll
|
[X86] Make lowering of intrinsics with rounding mode stricter so that only valid rounding modes are lowered. Update tests accordingly
|
2019-03-10 17:20:45 +00:00 |
|
avx512-fma-intrinsics.ll
|
[X86] Add the rounding control operand to the printing for some scalar FMA instructions.
|
2019-04-21 07:12:56 +00:00 |
|
avx512-fma.ll
|
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
|
2019-06-25 10:51:15 +00:00 |
|
avx512-fsel.ll
|
…
|
|
|
avx512-gather-scatter-intrin-deprecated.ll
|
…
|
|
|
avx512-gather-scatter-intrin.ll
|
…
|
|
|
avx512-gfni-intrinsics.ll
|
…
|
|
|
avx512-hadd-hsub.ll
|
[X86][AVX] Fold extract_subvector(broadcast(x)) -> broadcast(x) iff x has one use
|
2019-04-26 18:02:14 +00:00 |
|
avx512-i1test.ll
|
…
|
|
|
avx512-inc-dec.ll
|
…
|
|
|
avx512-insert-extract.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
avx512-insert-extract_i1.ll
|
…
|
|
|
avx512-intel-ocl.ll
|
…
|
|
|
avx512-intrinsics-canonical.ll
|
…
|
|
|
avx512-intrinsics-fast-isel.ll
|
[X86] Cleanups and safety checks around the isFNEG
|
2019-06-24 17:28:26 +00:00 |
|
avx512-intrinsics-upgrade.ll
|
[DAGCombiner] Replace masked loads with a zero mask with the passthru value
|
2019-06-02 18:58:46 +00:00 |
|
avx512-intrinsics-x86_64.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
avx512-intrinsics.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
avx512-load-store.ll
|
…
|
|
|
avx512-load-trunc-store-i1.ll
|
…
|
|
|
avx512-logic.ll
|
…
|
|
|
avx512-mask-op.ll
|
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
|
2019-06-25 10:51:15 +00:00 |
|
avx512-mask-spills.ll
|
…
|
|
|
avx512-mask-zext-bugfix.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
avx512-masked-memop-64-32.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
avx512-masked_memop-16-8.ll
|
[X86] Improve the type checking in isLegalMaskedLoad and isLegalMaskedGather.
|
2019-03-08 07:33:43 +00:00 |
|
avx512-memfold.ll
|
…
|
|
|
avx512-mov.ll
|
…
|
|
|
avx512-nontemporal.ll
|
…
|
|
|
avx512-pmovxrm.ll
|
…
|
|
|
avx512-regcall-Mask.ll
|
…
|
|
|
avx512-regcall-NoMask.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
avx512-rndscale.ll
|
…
|
|
|
avx512-rotate.ll
|
…
|
|
|
avx512-scalar.ll
|
…
|
|
|
avx512-scalarIntrinsics.ll
|
…
|
|
|
avx512-scalar_mask.ll
|
…
|
|
|
avx512-select.ll
|
[x86] remove whitespace; NFC
|
2019-06-27 20:37:12 +00:00 |
|
avx512-shift.ll
|
…
|
|
|
avx512-skx-insert-subvec.ll
|
…
|
|
|
avx512-trunc-widen.ll
|
[x86] split 256-bit store of concatenated vectors
|
2019-06-04 16:40:04 +00:00 |
|
avx512-trunc.ll
|
[x86] split 256-bit store of concatenated vectors
|
2019-06-04 16:40:04 +00:00 |
|
avx512-unsafe-fp-math.ll
|
…
|
|
|
avx512-vbroadcast.ll
|
[X86] Fix some tests using fcmp with undef arguments
|
2019-03-29 17:20:27 +00:00 |
|
avx512-vbroadcasti128.ll
|
…
|
|
|
avx512-vbroadcasti256.ll
|
…
|
|
|
avx512-vec-cmp.ll
|
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
|
2019-06-25 10:51:15 +00:00 |
|
avx512-vec3-crash.ll
|
…
|
|
|
avx512-vpclmulqdq.ll
|
…
|
|
|
avx512-vpermv3-commute.ll
|
…
|
|
|
avx512-vpternlog-commute.ll
|
…
|
|
|
avx512-vselect-crash.ll
|
…
|
|
|
avx512-vselect.ll
|
…
|
|
|
avx512bf16-intrinsics.ll
|
[X86] Regenerate intrinsics tests. NFCI.
|
2019-07-11 10:40:23 +00:00 |
|
avx512bf16-vl-intrinsics.ll
|
[CodeGen] Move X86 tests under the X86 directory
|
2019-05-06 10:21:17 +00:00 |
|
avx512bw-arith.ll
|
…
|
|
|
avx512bw-intrinsics-canonical.ll
|
…
|
|
|
avx512bw-intrinsics-fast-isel.ll
|
…
|
|
|
avx512bw-intrinsics-upgrade.ll
|
…
|
|
|
avx512bw-intrinsics.ll
|
[X86] Restore the pavg intrinsics.
|
2019-04-15 17:17:35 +00:00 |
|
avx512bw-mask-op.ll
|
…
|
|
|
avx512bw-mov.ll
|
…
|
|
|
avx512bw-vec-cmp.ll
|
…
|
|
|
avx512bw-vec-test-testn.ll
|
…
|
|
|
avx512bwvl-arith.ll
|
…
|
|
|
avx512bwvl-intrinsics-canonical.ll
|
…
|
|
|
avx512bwvl-intrinsics-fast-isel.ll
|
…
|
|
|
avx512bwvl-intrinsics-upgrade.ll
|
…
|
|
|
avx512bwvl-intrinsics.ll
|
[X86] Restore the pavg intrinsics.
|
2019-04-15 17:17:35 +00:00 |
|
avx512bwvl-mov.ll
|
…
|
|
|
avx512bwvl-vec-cmp.ll
|
…
|
|
|
avx512bwvl-vec-test-testn.ll
|
…
|
|
|
avx512cd-intrinsics-fast-isel.ll
|
…
|
|
|
avx512cd-intrinsics-upgrade.ll
|
…
|
|
|
avx512cd-intrinsics.ll
|
…
|
|
|
avx512cdvl-intrinsics-upgrade.ll
|
…
|
|
|
avx512cdvl-intrinsics.ll
|
…
|
|
|
avx512dq-intrinsics-fast-isel.ll
|
…
|
|
|
avx512dq-intrinsics-upgrade.ll
|
[X86] Make lowering of intrinsics with rounding mode stricter so that only valid rounding modes are lowered. Update tests accordingly
|
2019-03-10 17:20:45 +00:00 |
|
avx512dq-intrinsics.ll
|
[X86] Make lowering of intrinsics with rounding mode stricter so that only valid rounding modes are lowered. Update tests accordingly
|
2019-03-10 17:20:45 +00:00 |
|
avx512dq-mask-op.ll
|
…
|
|
|
avx512dqvl-intrinsics-fast-isel.ll
|
…
|
|
|
avx512dqvl-intrinsics-upgrade.ll
|
[X86][AVX] concat_vectors(scalar_to_vector(x),scalar_to_vector(x)) --> broadcast(x)
|
2019-02-23 18:34:05 +00:00 |
|
avx512dqvl-intrinsics.ll
|
[X86] Correct v4f32->v2i64 cvt(t)ps2(u)qq memory isel patterns
|
2019-07-01 19:01:37 +00:00 |
|
avx512er-intrinsics.ll
|
…
|
|
|
avx512f-256-set0.mir
|
[X86] Fix machineverifier error on avx512f-256-set0.mir
|
2019-05-29 17:02:27 +00:00 |
|
avx512f-vec-test-testn.ll
|
…
|
|
|
avx512ifma-intrinsics-fast-isel.ll
|
…
|
|
|
avx512ifma-intrinsics-upgrade.ll
|
[X86][AVX] EltsFromConsecutiveLoads - Add BROADCAST lowering support
|
2019-02-19 15:57:09 +00:00 |
|
avx512ifma-intrinsics.ll
|
[X86][AVX] EltsFromConsecutiveLoads - Add BROADCAST lowering support
|
2019-02-19 15:57:09 +00:00 |
|
avx512ifmavl-intrinsics-fast-isel.ll
|
…
|
|
|
avx512ifmavl-intrinsics-upgrade.ll
|
…
|
|
|
avx512ifmavl-intrinsics.ll
|
…
|
|
|
avx512vbmi-intrinsics-fast-isel.ll
|
…
|
|
|
avx512vbmi-intrinsics-upgrade.ll
|
…
|
|
|
avx512vbmi-intrinsics.ll
|
…
|
|
|
avx512vbmi2-intrinsics-fast-isel.ll
|
…
|
|
|
avx512vbmi2-intrinsics-upgrade.ll
|
…
|
|
|
avx512vbmi2-intrinsics.ll
|
…
|
|
|
avx512vbmi2vl-intrinsics-fast-isel.ll
|
…
|
|
|
avx512vbmi2vl-intrinsics-upgrade.ll
|
…
|
|
|
avx512vbmi2vl-intrinsics.ll
|
…
|
|
|
avx512vbmivl-intrinsics-fast-isel.ll
|
…
|
|
|
avx512vbmivl-intrinsics-upgrade.ll
|
…
|
|
|
avx512vbmivl-intrinsics.ll
|
…
|
|
|
avx512vl-arith.ll
|
…
|
|
|
avx512vl-intrinsics-canonical.ll
|
…
|
|
|
avx512vl-intrinsics-fast-isel.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to X86/avx512vl-intrinsics-fast-isel.ll X86/combine-fabs.ll"
|
2019-06-13 19:24:34 +00:00 |
|
avx512vl-intrinsics-upgrade.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
avx512vl-intrinsics.ll
|
…
|
|
|
avx512vl-logic.ll
|
…
|
|
|
avx512vl-mov.ll
|
…
|
|
|
avx512vl-nontemporal.ll
|
…
|
|
|
avx512vl-vbroadcast.ll
|
…
|
|
|
avx512vl-vec-cmp.ll
|
…
|
|
|
avx512vl-vec-masked-cmp.ll
|
…
|
|
|
avx512vl-vec-test-testn.ll
|
…
|
|
|
avx512vl-vpclmulqdq.ll
|
…
|
|
|
avx512vl_vnni-intrinsics-upgrade.ll
|
…
|
|
|
avx512vl_vnni-intrinsics.ll
|
…
|
|
|
avx512vlcd-intrinsics-fast-isel.ll
|
…
|
|
|
avx512vlvp2intersect-intrinsics.ll
|
[X86] Regenerate intrinsics tests. NFCI.
|
2019-07-11 10:40:23 +00:00 |
|
avx512vnni-intrinsics-upgrade.ll
|
…
|
|
|
avx512vnni-intrinsics.ll
|
…
|
|
|
avx512vp2intersect-intrinsics.ll
|
[X86] Regenerate intrinsics tests. NFCI.
|
2019-07-11 10:40:23 +00:00 |
|
avx512vpopcntdq-intrinsics.ll
|
…
|
|
|
backpropmask.ll
|
…
|
|
|
bad-tls-fold.mir
|
…
|
|
|
barrier-sse.ll
|
…
|
|
|
barrier.ll
|
…
|
|
|
base-pointer-and-cmpxchg.ll
|
…
|
|
|
basic-promote-integers.ll
|
…
|
|
|
bb_rotate.ll
|
[MBP] Factor out function hasViableTopFallthrough and enhancement
|
2019-02-22 18:04:37 +00:00 |
|
bc-extract.ll
|
…
|
|
|
bigstructret.ll
|
…
|
|
|
bigstructret2.ll
|
…
|
|
|
bit-piece-comment.ll
|
…
|
|
|
bit-test-shift.ll
|
…
|
|
|
bitcast-and-setcc-128.ll
|
…
|
|
|
bitcast-and-setcc-256.ll
|
[X86][AVX] combineBitcastvxi1 - peek through bitops to determine size of original vector
|
2019-05-26 10:54:23 +00:00 |
|
bitcast-and-setcc-512.ll
|
[X86][SSE] SimplifyDemandedBitsForTargetNode - Add initial PACKSS support
|
2019-04-07 10:40:01 +00:00 |
|
bitcast-i256.ll
|
…
|
|
|
bitcast-int-to-vector-bool-sext.ll
|
[X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(concat_vectors(x,y),c)
|
2019-07-04 10:17:10 +00:00 |
|
bitcast-int-to-vector-bool-zext.ll
|
[X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(concat_vectors(x,y),c)
|
2019-07-04 10:17:10 +00:00 |
|
bitcast-int-to-vector-bool.ll
|
[X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(concat_vectors(x,y),c)
|
2019-07-04 10:17:10 +00:00 |
|
bitcast-int-to-vector.ll
|
…
|
|
|
bitcast-mmx.ll
|
…
|
|
|
bitcast-setcc-128.ll
|
[X86][SSE] SimplifyDemandedBitsForTargetNode - Add initial PACKSS support
|
2019-04-07 10:40:01 +00:00 |
|
bitcast-setcc-256.ll
|
Recommit r358887 "[TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits bitcast handling"
|
2019-05-13 04:03:35 +00:00 |
|
bitcast-setcc-512.ll
|
[X86][AVX] truncateVectorWithPACK - avoid bitcasted shuffles
|
2019-06-26 09:50:11 +00:00 |
|
bitcast-vector-bool.ll
|
[X86][AVX] truncateVectorWithPACK - avoid bitcasted shuffles
|
2019-06-26 09:50:11 +00:00 |
|
bitcast.ll
|
…
|
|
|
bitcast2.ll
|
…
|
|
|
bitcnt-false-dep.ll
|
…
|
|
|
bitreverse.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
block-placement.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
block-placement.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
bmi-intrinsics-fast-isel-x86_64.ll
|
…
|
|
|
bmi-intrinsics-fast-isel.ll
|
…
|
|
|
bmi-x86_64.ll
|
…
|
|
|
bmi.ll
|
[X86] Add patterns with and_flag_nocf for BLSI and TBM instructions.
|
2019-07-10 22:44:32 +00:00 |
|
bmi2-x86_64.ll
|
…
|
|
|
bmi2.ll
|
…
|
|
|
bool-ext-inc.ll
|
…
|
|
|
bool-math.ll
|
[X86] Enable 8-bit OR with disjoint bits to convert to LEA
|
2019-03-05 18:37:33 +00:00 |
|
bool-simplify.ll
|
…
|
|
|
bool-vector.ll
|
[X86][SSE] Extract i1 elements from vXi1 bool vectors
|
2019-05-01 10:02:22 +00:00 |
|
bool-zext.ll
|
…
|
|
|
br-fold.ll
|
…
|
|
|
branchfolding-catchpads.ll
|
…
|
|
|
branchfolding-debugloc.ll
|
…
|
|
|
branchfolding-landingpads.ll
|
…
|
|
|
branchfolding-undef.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
brcond.ll
|
…
|
|
|
break-anti-dependencies.ll
|
…
|
|
|
break-false-dep.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
broadcast-elm-cross-splat-vec.ll
|
[X86][AVX] X86ISD::PERMV/PERMV3 node types can never fold index ops
|
2019-04-16 19:18:53 +00:00 |
|
broadcastm-lowering.ll
|
…
|
|
|
bss_pagealigned.ll
|
…
|
|
|
bswap-inline-asm.ll
|
…
|
|
|
bswap-rotate.ll
|
…
|
|
|
bswap-vector.ll
|
…
|
|
|
bswap-wide-int.ll
|
…
|
|
|
bswap.ll
|
…
|
|
|
bswap_tree.ll
|
…
|
|
|
bswap_tree2.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
bt.ll
|
[x86] make 8-bit shl undesirable
|
2019-04-08 13:58:50 +00:00 |
|
btc_bts_btr.ll
|
[TargetLowering][X86] Teach SimplifyDemandedBits to use ShrinkDemandedOp on ISD::SHL nodes.
|
2019-04-12 06:49:28 +00:00 |
|
btq.ll
|
…
|
|
|
bug26810.ll
|
…
|
|
|
bug37521.ll
|
…
|
|
|
build-vector-128.ll
|
…
|
|
|
build-vector-256.ll
|
…
|
|
|
build-vector-512.ll
|
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
|
2019-07-02 17:51:02 +00:00 |
|
buildvec-extract.ll
|
…
|
|
|
buildvec-insertvec.ll
|
[X86] Make movsd commutable to shufpd with a 0x02 immediate on pre-SSE4.1 targets.
|
2019-07-08 06:52:43 +00:00 |
|
bypass-slow-division-32.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
bypass-slow-division-64.ll
|
…
|
|
|
bypass-slow-division-tune.ll
|
…
|
|
|
byval-align.ll
|
…
|
|
|
byval-callee-cleanup.ll
|
…
|
|
|
byval.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
byval2.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
byval3.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
byval4.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
byval5.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
byval6.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
byval7.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
cache-intrinsic.ll
|
…
|
|
|
call-imm.ll
|
…
|
|
|
call-push.ll
|
…
|
|
|
call-site-info-output.ll
|
[ISEL][X86] Tracking of registers that forward call arguments
|
2019-06-27 10:51:15 +00:00 |
|
callbr-asm-bb-exports.ll
|
[X86] Add test case for r361177.
|
2019-05-20 17:37:52 +00:00 |
|
callbr-asm-blockplacement.ll
|
…
|
|
|
callbr-asm-branch-folding.ll
|
…
|
|
|
callbr-asm-destinations.ll
|
…
|
|
|
callbr-asm-errors.ll
|
…
|
|
|
callbr-asm-outputs.ll
|
…
|
|
|
callbr-asm.ll
|
…
|
|
|
cas.ll
|
…
|
|
|
cast-vsel.ll
|
[x86] split 256-bit vector selects if operands are vector concats
|
2019-06-16 14:04:49 +00:00 |
|
catch.ll
|
…
|
|
|
catchpad-dynamic-alloca.ll
|
…
|
|
|
catchpad-lifetime.ll
|
…
|
|
|
catchpad-realign-savexmm.ll
|
…
|
|
|
catchpad-regmask.ll
|
…
|
|
|
catchpad-reuse.ll
|
…
|
|
|
catchpad-weight.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
catchret-empty-fallthrough.ll
|
…
|
|
|
catchret-fallthrough.ll
|
…
|
|
|
catchret-regmask.ll
|
…
|
|
|
cfi-inserter-cfg-with-merge.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
cfi-inserter-check-order.ll
|
…
|
|
|
cfi-inserter-noreturnblock.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
cfi-inserter-verify-inconsistent-offset.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
cfi-inserter-verify-inconsistent-register.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
cfi-xmm.ll
|
…
|
|
|
cfi.ll
|
…
|
|
|
cfstring.ll
|
…
|
|
|
cgp-usubo.ll
|
[X86] Pre commit test cases for D64574. Along with a test case for PR42571. NFC
|
2019-07-11 18:19:27 +00:00 |
|
chain_order.ll
|
…
|
|
|
change-compare-stride-1.ll
|
…
|
|
|
change-compare-stride-trickiness-0.ll
|
…
|
|
|
change-compare-stride-trickiness-1.ll
|
…
|
|
|
change-compare-stride-trickiness-2.ll
|
…
|
|
|
change-unsafe-fp-math.ll
|
…
|
|
|
cldemote-intrinsic.ll
|
…
|
|
|
cleanuppad-inalloca.ll
|
…
|
|
|
cleanuppad-large-codemodel.ll
|
…
|
|
|
cleanuppad-realign.ll
|
…
|
|
|
clear-highbits.ll
|
…
|
|
|
clear-lowbits.ll
|
…
|
|
|
clear_upper_vector_element_bits.ll
|
…
|
|
|
clflushopt.ll
|
…
|
|
|
clwb.ll
|
…
|
|
|
clz.ll
|
[x86] regenerate checks; NFC
|
2019-02-21 15:30:28 +00:00 |
|
clzero.ll
|
[X86] Remove CustomInserter pseudos for MONITOR/MONITORX/CLZERO. Use custom instruction selection instead.
|
2019-04-03 23:28:30 +00:00 |
|
cmov-double.ll
|
[x86] auto-generate complete checks for test; NFC
|
2019-03-22 15:33:47 +00:00 |
|
cmov-fp.ll
|
…
|
|
|
cmov-into-branch.ll
|
…
|
|
|
cmov-promotion.ll
|
Teach the DAGCombine to fold this pattern(c1 and c2 is constant).
|
2019-06-26 05:12:53 +00:00 |
|
cmov.ll
|
[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
|
2019-06-13 13:56:19 +00:00 |
|
cmovcmov.ll
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
cmp-fast-isel.ll
|
…
|
|
|
cmp.ll
|
[X86] When promoting i16 compare with immediate to i32, try to use sign_extend for eq/ne if the input is truncated from a type with enough sign its.
|
2019-06-10 04:50:12 +00:00 |
|
cmpxchg-clobber-flags.ll
|
…
|
|
|
cmpxchg-i1.ll
|
…
|
|
|
cmpxchg-i128-i1.ll
|
…
|
|
|
cmpxchg8b.ll
|
[X86] Add CMPXCHG8B feature flag. Set it for all CPUs except i386/i486 including 'generic'. Disable use of CMPXCHG8B when this flag isn't set.
|
2019-03-20 23:35:49 +00:00 |
|
cmpxchg8b_alloca_regalloc_handling.ll
|
…
|
|
|
cmpxchg16b.ll
|
…
|
|
|
coal-sections.ll
|
…
|
|
|
coalesce-dbg-value-subreg-rewrite.mir
|
…
|
|
|
coalesce-dead-lanes.mir
|
…
|
|
|
coalesce-esp.ll
|
…
|
|
|
coalesce-implicitdef.ll
|
…
|
|
|
coalesce_commute_movsd.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
coalesce_commute_subreg.ll
|
…
|
|
|
coalescer-commute1.ll
|
…
|
|
|
coalescer-commute2.ll
|
…
|
|
|
coalescer-commute3.ll
|
…
|
|
|
coalescer-commute4.ll
|
…
|
|
|
coalescer-commute5.ll
|
…
|
|
|
coalescer-cross.ll
|
…
|
|
|
coalescer-dce.ll
|
…
|
|
|
coalescer-dce2.ll
|
…
|
|
|
coalescer-identity.ll
|
…
|
|
|
coalescer-remat.ll
|
…
|
|
|
coalescer-subreg.ll
|
…
|
|
|
coalescer-win64.ll
|
…
|
|
|
code-model-elf-memset.ll
|
…
|
|
|
code-model-elf.ll
|
[X86] Fix tls variable lowering issue with large code model
|
2019-02-24 19:33:37 +00:00 |
|
code-model-kernel.ll
|
…
|
|
|
code_placement.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
code_placement_align_all.ll
|
…
|
|
|
code_placement_cold_loop_blocks.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
code_placement_eh.ll
|
…
|
|
|
code_placement_ignore_succ_in_inner_loop.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
code_placement_loop_rotation.ll
|
…
|
|
|
code_placement_loop_rotation2.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
code_placement_loop_rotation3.ll
|
…
|
|
|
code_placement_no_header_change.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
codegen-prepare-addrmode-sext.ll
|
…
|
|
|
codegen-prepare-cast.ll
|
…
|
|
|
codegen-prepare-crash.ll
|
…
|
|
|
codegen-prepare-extload.ll
|
…
|
|
|
codegen-prepare-replacephi.mir
|
test/CodeGen/X86/codegen-prepare-replacephi.mir requires a default triple
|
2019-03-27 20:43:47 +00:00 |
|
codegen-prepare-uaddo.ll
|
[CGP] add special-cases to form unsigned add with overflow (PR40486)
|
2019-02-24 15:31:27 +00:00 |
|
codegen-prepare.ll
|
…
|
|
|
codemodel.ll
|
[X86] Use PC-relative mode for the kernel code model
|
2019-04-13 21:39:28 +00:00 |
|
coff-comdat.ll
|
…
|
|
|
coff-comdat2.ll
|
…
|
|
|
coff-comdat3.ll
|
…
|
|
|
coff-feat00.ll
|
…
|
|
|
coff-no-dead-strip.ll
|
…
|
|
|
coff-weak.ll
|
…
|
|
|
coldcc64.ll
|
…
|
|
|
combine-64bit-vec-binop.ll
|
…
|
|
|
combine-abs.ll
|
…
|
|
|
combine-adc.ll
|
[X86] Merge ISD::ADD/SUB nodes into X86ISD::ADD/SUB equivalents (PR40483)
|
2019-02-25 11:19:37 +00:00 |
|
combine-add-ssat.ll
|
…
|
|
|
combine-add-usat.ll
|
…
|
|
|
combine-add.ll
|
[DAGCombiner][X86][AArch64][AMDGPU] (x + C) - y -> (x - y) + C fold. Try 3
|
2019-05-30 20:36:54 +00:00 |
|
combine-addo.ll
|
[DAGCombiner] Enable UADDO/USUBO vector combine support
|
2019-03-06 16:11:03 +00:00 |
|
combine-adx.ll
|
…
|
|
|
combine-and.ll
|
…
|
|
|
combine-avx-intrinsics.ll
|
…
|
|
|
combine-avx2-intrinsics.ll
|
…
|
|
|
combine-bitreverse.ll
|
[SelectionDAG] computeKnownBits - support constant pool values from target
|
2019-05-24 10:03:11 +00:00 |
|
combine-bitselect.ll
|
[X86][AVX] getTargetConstantBitsFromNode - extract bits from X86ISD::SUBV_BROADCAST
|
2019-04-10 16:24:47 +00:00 |
|
combine-bswap.ll
|
…
|
|
|
combine-concatvectors.ll
|
…
|
|
|
combine-fabs.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to X86/avx512vl-intrinsics-fast-isel.ll X86/combine-fabs.ll"
|
2019-06-13 19:24:34 +00:00 |
|
combine-fcopysign.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to X86/combine-fcopysign.ll X86/dag-fmf-cse.ll X86/fast-isel-fneg.ll X86/fdiv.ll"
|
2019-06-13 19:24:38 +00:00 |
|
combine-lds.ll
|
…
|
|
|
combine-mul.ll
|
[DAGCombine] visitMUL - allow shift by zero in MulByConstant.
|
2019-06-24 12:47:17 +00:00 |
|
combine-mulo.ll
|
[DAGCombiner] Enable SMULO/UMULO vector combine support (PR40442)
|
2019-03-06 11:04:21 +00:00 |
|
combine-multiplies.ll
|
[DAG] Refactor DAGCombiner::ReassociateOps
|
2019-04-29 17:50:10 +00:00 |
|
combine-or.ll
|
…
|
|
|
combine-pmuldq.ll
|
[TargetLowering] SimplifyDemandedBits ZERO_EXTEND_VECTOR_INREG -> ANY_EXTEND_VECTOR_INREG
|
2019-06-25 12:57:43 +00:00 |
|
combine-rotates.ll
|
…
|
|
|
combine-sbb.ll
|
[x86] add test for sub-with-flags opportunity (PR40483); NFC
|
2019-07-14 14:08:39 +00:00 |
|
combine-sdiv.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
combine-select.ll
|
…
|
|
|
combine-sext-in-reg.ll
|
…
|
|
|
combine-shl.ll
|
[DAGCombiner] Support (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C)) non-uniform folds.
|
2019-06-20 14:42:27 +00:00 |
|
combine-smax.ll
|
…
|
|
|
combine-smin.ll
|
…
|
|
|
combine-sra.ll
|
[x86] split more v8f32/v8i32 shuffles in lowering
|
2019-02-18 16:46:12 +00:00 |
|
combine-srem.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
combine-srl.ll
|
[x86] split more v8f32/v8i32 shuffles in lowering
|
2019-02-18 16:46:12 +00:00 |
|
combine-sse41-intrinsics.ll
|
…
|
|
|
combine-sub-ssat.ll
|
…
|
|
|
combine-sub-usat.ll
|
…
|
|
|
combine-sub.ll
|
…
|
|
|
combine-subo.ll
|
[DAGCombiner] Enable UADDO/USUBO vector combine support
|
2019-03-06 16:11:03 +00:00 |
|
combine-testm-and.ll
|
…
|
|
|
combine-udiv.ll
|
[TargetLowering] SimplifyDemandedVectorElts - add shift/rotate support.
|
2019-06-27 14:25:54 +00:00 |
|
combine-umax.ll
|
…
|
|
|
combine-umin.ll
|
…
|
|
|
combine-urem.ll
|
…
|
|
|
commandline-metadata.ll
|
…
|
|
|
commute-3dnow.ll
|
…
|
|
|
commute-blend-avx2.ll
|
…
|
|
|
commute-blend-sse41.ll
|
[X86][SSE] Use pblendw for v4i32/v2i64 during isel.
|
2019-02-24 19:23:41 +00:00 |
|
commute-clmul.ll
|
…
|
|
|
commute-fcmp.ll
|
…
|
|
|
commute-intrinsic.ll
|
…
|
|
|
commute-two-addr.ll
|
…
|
|
|
commute-vpclmulqdq-avx.ll
|
…
|
|
|
commute-vpclmulqdq-avx512.ll
|
…
|
|
|
commute-xop.ll
|
…
|
|
|
commuted-blend-mask.ll
|
…
|
|
|
compact-unwind.ll
|
…
|
|
|
compare-add.ll
|
…
|
|
|
compare-global.ll
|
…
|
|
|
compare-inf.ll
|
…
|
|
|
compare_folding.ll
|
…
|
|
|
compiler_used.ll
|
…
|
|
|
complex-asm.ll
|
…
|
|
|
complex-fastmath.ll
|
…
|
|
|
complex-fca.ll
|
…
|
|
|
computeKnownBits_urem.ll
|
…
|
|
|
condbr_if.ll
|
…
|
|
|
condbr_switch.ll
|
…
|
|
|
conditional-indecrement.ll
|
…
|
|
|
conditional-tailcall-samedest.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
conditional-tailcall.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
consecutive-load-shuffle.ll
|
…
|
|
|
const-base-addr.ll
|
…
|
|
|
const-shift-of-constmasked.ll
|
[NFC][CodeGen][X86][AArch64] Add and-const-mask + const-shift pattern tests
|
2019-05-14 20:17:04 +00:00 |
|
constant-combines.ll
|
[DAGCombine] Prune unnused nodes.
|
2019-03-29 17:35:56 +00:00 |
|
constant-hoisting-and.ll
|
…
|
|
|
constant-hoisting-bfi.ll
|
…
|
|
|
constant-hoisting-cmp.ll
|
…
|
|
|
constant-hoisting-optnone.ll
|
…
|
|
|
constant-hoisting-shift-immediate.ll
|
…
|
|
|
constant-pool-remat-0.ll
|
…
|
|
|
constant-pool-sharing.ll
|
…
|
|
|
constpool.ll
|
…
|
|
|
constrained-fp80-trunc-ext.ll
|
[FPEnv] Lower STRICT_FP_EXTEND and STRICT_FP_ROUND nodes in preprocess phase of ISelLowering to mirror non-strict nodes on x86.
|
2019-06-14 16:28:55 +00:00 |
|
constructor.ll
|
…
|
|
|
convert-2-addr-3-addr-inc64.ll
|
…
|
|
|
copy-eflags.ll
|
[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
|
2019-06-13 13:56:19 +00:00 |
|
copy-propagation.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
copysign-constant-magnitude.ll
|
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
|
2019-07-02 17:51:02 +00:00 |
|
cpus-amd-no-x86_64.ll
|
…
|
|
|
cpus-amd.ll
|
[X86] AMD znver2 enablement
|
2019-02-26 16:55:10 +00:00 |
|
cpus-intel-no-x86_64.ll
|
…
|
|
|
cpus-intel.ll
|
[X86] -march=cooperlake (llvm)
|
2019-06-07 08:31:35 +00:00 |
|
cpus-no-x86_64.ll
|
…
|
|
|
cpus-other.ll
|
…
|
|
|
crash-O0.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
crash-lre-eliminate-dead-def.ll
|
…
|
|
|
crash-nosse.ll
|
…
|
|
|
crash.ll
|
…
|
|
|
critical-anti-dep-breaker.ll
|
…
|
|
|
critical-edge-split-2.ll
|
…
|
|
|
cse-add-with-overflow.ll
|
…
|
|
|
cstring.ll
|
…
|
|
|
ctor-priority-coff.ll
|
…
|
|
|
ctpop-combine.ll
|
[SDAG] expand ctpop != 1
|
2019-06-25 14:46:52 +00:00 |
|
cvt16.ll
|
…
|
|
|
cvtv2f32.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
cxx_tlscc64.ll
|
…
|
|
|
dag-fmf-cse.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to X86/combine-fcopysign.ll X86/dag-fmf-cse.ll X86/fast-isel-fneg.ll X86/fdiv.ll"
|
2019-06-13 19:24:38 +00:00 |
|
dag-merge-fast-accesses.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
dag-optnone.ll
|
…
|
|
|
dag-rauw-cse.ll
|
…
|
|
|
dag-update-nodetomatch.ll
|
…
|
|
|
dagcombine-and-setcc.ll
|
…
|
|
|
dagcombine-buildvector.ll
|
…
|
|
|
dagcombine-cse.ll
|
Recommit r358887 "[TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits bitcast handling"
|
2019-05-13 04:03:35 +00:00 |
|
dagcombine-select.ll
|
…
|
|
|
dagcombine-shifts.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
dagcombine-tokenfactor-limit-crash.ll
|
Recommit r360171: [DAGCombiner] Avoid creating large tokenfactors in visitTokenFactor.
|
2019-06-03 01:30:19 +00:00 |
|
dagcombine-unsafe-math.ll
|
…
|
|
|
darwin-bzero.ll
|
…
|
|
|
darwin-no-dead-strip.ll
|
…
|
|
|
darwin-preemption.ll
|
…
|
|
|
darwin-quote.ll
|
…
|
|
|
darwin-tls.ll
|
…
|
|
|
dbg-baseptr.ll
|
…
|
|
|
dbg-changes-codegen-branch-folding.ll
|
…
|
|
|
dbg-changes-codegen-branch-folding2.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
dbg-changes-codegen.ll
|
…
|
|
|
dbg-combine.ll
|
…
|
|
|
dbg-line-0-no-discriminator.ll
|
…
|
|
|
dbg-value-superreg-copy.mir
|
…
|
|
|
debug-loclists.ll
|
…
|
|
|
debug-nodebug-crash.ll
|
…
|
|
|
debuginfo-locations-dce.ll
|
…
|
|
|
debugloc-argsize.ll
|
…
|
|
|
debugloc-no-line-0.ll
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
deopt-bundles.ll
|
…
|
|
|
deopt-intrinsic-cconv.ll
|
…
|
|
|
deopt-intrinsic.ll
|
…
|
|
|
disable-tail-calls.ll
|
…
|
|
|
discontiguous-loops.ll
|
…
|
|
|
discriminate-mem-ops-missing-info.ll
|
[llvm] X86DiscriminateMemOps: insert debug info when missing
|
2019-05-10 00:12:51 +00:00 |
|
discriminate-mem-ops-skip-pfetch.ll
|
Skip over prefetches
|
2019-05-10 21:27:55 +00:00 |
|
discriminate-mem-ops.ll
|
…
|
|
|
div-rem-simplify.ll
|
…
|
|
|
div8.ll
|
…
|
|
|
divide-by-constant.ll
|
…
|
|
|
divide-windows-itanium.ll
|
…
|
|
|
divrem.ll
|
…
|
|
|
divrem8_ext.ll
|
…
|
|
|
dllexport-x86_64.ll
|
…
|
|
|
dllexport.ll
|
…
|
|
|
dllimport-x86_64.ll
|
…
|
|
|
dllimport.ll
|
…
|
|
|
dollar-name.ll
|
…
|
|
|
domain-reassignment-implicit-def.ll
|
…
|
|
|
domain-reassignment-test.ll
|
…
|
|
|
domain-reassignment.mir
|
[X86] Regenerate checks for domain-reassignment.mir
|
2019-04-15 05:22:47 +00:00 |
|
dont-trunc-store-double-to-float.ll
|
…
|
|
|
dropped_constructor.ll
|
…
|
|
|
dwarf-comp-dir.ll
|
…
|
|
|
dwarf-eh-prepare.ll
|
…
|
|
|
dwarf-headers.ll
|
…
|
|
|
dwarf-split-line-1.ll
|
…
|
|
|
dwarf-split-line-2.ll
|
…
|
|
|
dyn-stackalloc.ll
|
…
|
|
|
dyn_alloca_aligned.ll
|
…
|
|
|
dynamic-alloca-in-entry.ll
|
…
|
|
|
dynamic-alloca-lifetime.ll
|
…
|
|
|
dynamic-allocas-VLAs.ll
|
…
|
|
|
dynamic-regmask.ll
|
…
|
|
|
early-cfi-sections.ll
|
…
|
|
|
early-ifcvt-crash.ll
|
…
|
|
|
early-ifcvt.ll
|
…
|
|
|
eh-frame-unreachable.ll
|
…
|
|
|
eh-label.ll
|
…
|
|
|
eh-nolandingpads.ll
|
…
|
|
|
eh-null-personality.ll
|
…
|
|
|
eh-unknown.ll
|
…
|
|
|
eh_frame.ll
|
…
|
|
|
eip-addressing-i386.ll
|
…
|
|
|
element-wise-atomic-memory-intrinsics.ll
|
[Tests] Yet more combination of tests for unordered.atomic memset
|
2019-05-07 17:45:52 +00:00 |
|
elf-associated.ll
|
…
|
|
|
elf-comdat.ll
|
…
|
|
|
elf-comdat2.ll
|
…
|
|
|
emit-big-cst.ll
|
…
|
|
|
empty-function.ll
|
…
|
|
|
empty-functions.ll
|
…
|
|
|
empty-struct-return-type.ll
|
…
|
|
|
emutls-pic.ll
|
…
|
|
|
emutls-pie.ll
|
…
|
|
|
emutls.ll
|
…
|
|
|
emutls_generic.ll
|
…
|
|
|
enqcmd-intrinsics.ll
|
[X86] Add ENQCMD instructions
|
2019-05-30 03:59:16 +00:00 |
|
epilogue-cfi-fp.ll
|
…
|
|
|
epilogue-cfi-no-fp.ll
|
…
|
|
|
epilogue.ll
|
…
|
|
|
equiv_with_fndef.ll
|
…
|
|
|
equiv_with_vardef.ll
|
…
|
|
|
evex-to-vex-compress.mir
|
[X86] Remove MOVDI2SSrm/MOV64toSDrm/MOVSS2DImr/MOVSDto64mr CodeGenOnly instructions.
|
2019-06-18 03:23:15 +00:00 |
|
exception-label.ll
|
…
|
|
|
exedeps-movq.ll
|
[x86] scalarize extract element 0 of FP math
|
2019-02-28 19:47:04 +00:00 |
|
exedepsfix-broadcast.ll
|
…
|
|
|
expand-integer-x86_64-intrinsic-error.ll
|
…
|
|
|
expand-opaque-const.ll
|
…
|
|
|
expand-post-ra-pseudo.mir
|
…
|
|
|
expand-vr64-gr64-copy.mir
|
…
|
|
|
extend-set-cc-uses-dbg.ll
|
RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs
|
2019-03-19 19:01:34 +00:00 |
|
extend.ll
|
…
|
|
|
extended-fma-contraction.ll
|
…
|
|
|
extern_weak.ll
|
[COFF] Use COFF stubs for extern_weak functions
|
2019-05-07 23:06:21 +00:00 |
|
extmul64.ll
|
…
|
|
|
extmul128.ll
|
…
|
|
|
extract-bits.ll
|
[X86] X86DAGToDAGISel::matchBitExtract(): pattern c: truncation awareness
|
2019-06-26 12:19:47 +00:00 |
|
extract-combine.ll
|
…
|
|
|
extract-concat.ll
|
…
|
|
|
extract-extract.ll
|
…
|
|
|
extract-fp.ll
|
[X86] Combine fminnum/fmaxnum with non-nan operand to fmin/fmax
|
2019-05-25 16:44:29 +00:00 |
|
extract-insert.ll
|
[TargetLowering] SimplifyDemandedBits - use DemandedElts in bitcast handling
|
2019-04-08 20:59:38 +00:00 |
|
extract-lowbits.ll
|
[X86] X86DAGToDAGISel::matchBitExtract(): pattern c: truncation awareness
|
2019-06-26 12:19:47 +00:00 |
|
extract-store.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
extractelement-fp.ll
|
[DAGCombiner] try to move bitcast after extract_subvector
|
2019-05-12 14:43:20 +00:00 |
|
extractelement-from-arg.ll
|
…
|
|
|
extractelement-index.ll
|
…
|
|
|
extractelement-legalization-cycle.ll
|
…
|
|
|
extractelement-legalization-store-ordering.ll
|
…
|
|
|
extractelement-load.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
extractelement-shuffle.ll
|
…
|
|
|
extractps.ll
|
…
|
|
|
f16c-intrinsics-fast-isel.ll
|
…
|
|
|
f16c-intrinsics.ll
|
…
|
|
|
fabs.ll
|
…
|
|
|
fadd-combines.ll
|
…
|
|
|
fast-cc-callee-pops.ll
|
…
|
|
|
fast-cc-merge-stack-adj.ll
|
…
|
|
|
fast-cc-pass-in-regs.ll
|
…
|
|
|
fast-isel-abort-warm.ll
|
…
|
|
|
fast-isel-agg-constant.ll
|
…
|
|
|
fast-isel-args-fail.ll
|
…
|
|
|
fast-isel-args-fail2.ll
|
…
|
|
|
fast-isel-args.ll
|
…
|
|
|
fast-isel-atomic.ll
|
…
|
|
|
fast-isel-avoid-unnecessary-pic-base.ll
|
…
|
|
|
fast-isel-bail.ll
|
…
|
|
|
fast-isel-bc.ll
|
…
|
|
|
fast-isel-bitcasts-avx.ll
|
…
|
|
|
fast-isel-bitcasts-avx512.ll
|
…
|
|
|
fast-isel-bitcasts.ll
|
…
|
|
|
fast-isel-branch_weights.ll
|
…
|
|
|
fast-isel-call-bool.ll
|
…
|
|
|
fast-isel-call-cleanup.ll
|
…
|
|
|
fast-isel-call.ll
|
…
|
|
|
fast-isel-cmp-branch.ll
|
…
|
|
|
fast-isel-cmp-branch2.ll
|
…
|
|
|
fast-isel-cmp-branch3.ll
|
…
|
|
|
fast-isel-cmp.ll
|
…
|
|
|
fast-isel-constant.ll
|
…
|
|
|
fast-isel-constpool.ll
|
…
|
|
|
fast-isel-constrain-store-indexreg.ll
|
…
|
|
|
fast-isel-deadcode.ll
|
…
|
|
|
fast-isel-divrem-x86-64.ll
|
…
|
|
|
fast-isel-divrem.ll
|
…
|
|
|
fast-isel-double-half-convertion.ll
|
…
|
|
|
fast-isel-emutls.ll
|
…
|
|
|
fast-isel-expect.ll
|
…
|
|
|
fast-isel-extract.ll
|
…
|
|
|
fast-isel-float-half-convertion.ll
|
…
|
|
|
fast-isel-fneg-kill.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
fast-isel-fneg.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to X86/combine-fcopysign.ll X86/dag-fmf-cse.ll X86/fast-isel-fneg.ll X86/fdiv.ll"
|
2019-06-13 19:24:38 +00:00 |
|
fast-isel-fold-mem.ll
|
…
|
|
|
fast-isel-fptrunc-fpext.ll
|
…
|
|
|
fast-isel-gc-intrinsics.ll
|
[FastISel] Fix crash for gc.relocate lowring
|
2019-04-05 05:41:08 +00:00 |
|
fast-isel-gep.ll
|
…
|
|
|
fast-isel-gv.ll
|
…
|
|
|
fast-isel-i1.ll
|
…
|
|
|
fast-isel-int-float-conversion-x86-64.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
fast-isel-int-float-conversion.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
fast-isel-load-i1.ll
|
…
|
|
|
fast-isel-mem.ll
|
…
|
|
|
fast-isel-movsbl-indexreg.ll
|
…
|
|
|
fast-isel-nontemporal.ll
|
[X86] Don't emit MOVNTDQA loads from fast-isel without SSE4.1.
|
2019-05-11 04:19:33 +00:00 |
|
fast-isel-noplt-pic.ll
|
…
|
|
|
fast-isel-ret-ext.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
fast-isel-select-cmov.ll
|
…
|
|
|
fast-isel-select-cmov2.ll
|
…
|
|
|
fast-isel-select-cmp.ll
|
…
|
|
|
fast-isel-select-pseudo-cmov.ll
|
[X86] Add CMOV_FR32X/CMOV_FR64X pseudo instructions. Use them in fast isel to fix a machine verifier error after adding test cases.
|
2019-05-11 16:00:28 +00:00 |
|
fast-isel-select-sse.ll
|
…
|
|
|
fast-isel-select.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
fast-isel-sext-zext.ll
|
…
|
|
|
fast-isel-sext.ll
|
…
|
|
|
fast-isel-shift.ll
|
[X86] Enable 8-bit SHL to convert to LEA
|
2019-03-05 18:37:41 +00:00 |
|
fast-isel-sse12-fptoint.ll
|
…
|
|
|
fast-isel-stackcheck.ll
|
…
|
|
|
fast-isel-store.ll
|
[DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support
|
2019-07-11 14:45:03 +00:00 |
|
fast-isel-tailcall.ll
|
…
|
|
|
fast-isel-tls.ll
|
…
|
|
|
fast-isel-trunc-kill-subreg.ll
|
…
|
|
|
fast-isel-uint-float-conversion-x86-64.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
fast-isel-uint-float-conversion.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
fast-isel-vecload.ll
|
…
|
|
|
fast-isel-x32.ll
|
…
|
|
|
fast-isel-x86-64.ll
|
RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs
|
2019-03-19 19:01:34 +00:00 |
|
fast-isel-x86.ll
|
…
|
|
|
fast-isel.ll
|
…
|
|
|
fastcall-correct-mangling.ll
|
…
|
|
|
fastcc-2.ll
|
…
|
|
|
fastcc-byval.ll
|
…
|
|
|
fastcc-sret.ll
|
…
|
|
|
fastcc.ll
|
…
|
|
|
fastcc3struct.ll
|
…
|
|
|
fastisel-gep-promote-before-add.ll
|
…
|
|
|
fastisel-softfloat.ll
|
…
|
|
|
fastmath-float-half-conversion.ll
|
…
|
|
|
fcmove.ll
|
…
|
|
|
fcmp-constant.ll
|
[SelectionDAG] Add fcmp UNDEF handling to SelectionDAG::FoldSetCC
|
2019-04-05 14:56:21 +00:00 |
|
fdiv-combine-vec.ll
|
[DAGCombiner] try repeated fdiv divisor transform before building estimate (2nd try)
|
2019-05-02 15:02:08 +00:00 |
|
fdiv-combine.ll
|
adding more fmf propagation for selects plus updated tests
|
2019-06-15 04:53:51 +00:00 |
|
fdiv.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to X86/combine-fcopysign.ll X86/dag-fmf-cse.ll X86/fast-isel-fneg.ll X86/fdiv.ll"
|
2019-06-13 19:24:38 +00:00 |
|
fentry-insertion.ll
|
…
|
|
|
field-extract-use-trunc.ll
|
…
|
|
|
fildll.ll
|
…
|
|
|
file-directive.ll
|
[llvm-readobj] Change -long-option to --long-option in tests. NFC
|
2019-05-01 05:27:20 +00:00 |
|
file-source-filename.ll
|
…
|
|
|
finite-libcalls.ll
|
…
|
|
|
fixed-stack-di-mir.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
fixup-bw-copy.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
fixup-bw-copy.mir
|
…
|
|
|
fixup-bw-inst.ll
|
…
|
|
|
fixup-bw-inst.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
fixup-lea.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
flags-copy-lowering.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
float-asmprint.ll
|
…
|
|
|
float-conv-elim.ll
|
…
|
|
|
floor-soft-float.ll
|
…
|
|
|
fltused.ll
|
…
|
|
|
fltused_function_pointer.ll
|
…
|
|
|
fltused_math.ll
|
…
|
|
|
fma-commute-x86.ll
|
…
|
|
|
fma-do-not-commute.ll
|
…
|
|
|
fma-fneg-combine.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma-fneg-combine.ll"
|
2019-06-13 19:24:41 +00:00 |
|
fma-intrinsics-canonical.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to X86/fma-intrinsics-canonical.ll"
|
2019-06-13 19:24:47 +00:00 |
|
fma-intrinsics-fast-isel.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to some X86/ and XCore/ tests."
|
2019-06-13 19:24:51 +00:00 |
|
fma-intrinsics-phi-213-to-231.ll
|
…
|
|
|
fma-intrinsics-x86-upgrade.ll
|
…
|
|
|
fma-intrinsics-x86.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma-intrinsics-x86.ll"
|
2019-06-13 19:24:57 +00:00 |
|
fma-phi-213-to-231.ll
|
…
|
|
|
fma-scalar-combine.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma-scalar-combine.ll"
|
2019-06-13 19:25:00 +00:00 |
|
fma-scalar-memfold.ll
|
…
|
|
|
fma.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
fma4-commute-x86.ll
|
…
|
|
|
fma4-fneg-combine.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma4-fneg-combine.ll"
|
2019-06-13 19:25:03 +00:00 |
|
fma4-intrinsics-x86-upgrade.ll
|
…
|
|
|
fma4-intrinsics-x86.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma4-intrinsics-x86.ll"
|
2019-06-13 19:24:54 +00:00 |
|
fma4-intrinsics-x86_64-folded-load.ll
|
…
|
|
|
fma4-scalar-memfold.ll
|
…
|
|
|
fma_patterns.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma_patterns.ll"
|
2019-06-13 19:25:06 +00:00 |
|
fma_patterns_wide.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma_patterns_wide.ll"
|
2019-06-13 19:25:09 +00:00 |
|
fmaddsub-combine.ll
|
…
|
|
|
fmaxnum.ll
|
[X86] Combine fminnum/fmaxnum with non-nan operand to fmin/fmax
|
2019-05-25 16:44:29 +00:00 |
|
fmf-flags.ll
|
…
|
|
|
fmf-propagation.ll
|
Propagate fmf for setcc in SDAG for select folds
|
2019-06-03 21:53:26 +00:00 |
|
fminnum.ll
|
[X86] Combine fminnum/fmaxnum with non-nan operand to fmin/fmax
|
2019-05-25 16:44:29 +00:00 |
|
fmsubadd-combine.ll
|
…
|
|
|
fmul-combines.ll
|
Move three folds for FADD, FSUB and FMUL in the DAG combiner away from Unsafe to more aligned checks that reflect context
|
2019-07-10 18:23:26 +00:00 |
|
fnabs.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to fmul-combines.ll fnabs.ll"
|
2019-06-13 19:25:12 +00:00 |
|
fold-add.ll
|
…
|
|
|
fold-and-shift-x86_64.ll
|
[X86] Teach foldMaskedShiftToScaledMask to look through an any_extend from i32 to i64 between the and & shl
|
2019-04-10 21:42:08 +00:00 |
|
fold-and-shift.ll
|
[X86] Prevent folding a load into an AND if that AND is really a ZEXT_INREG that should use movzx.
|
2019-04-24 19:28:38 +00:00 |
|
fold-call-2.ll
|
…
|
|
|
fold-call-3.ll
|
[X86] If PreprocessISelDAG reorders a load before a call, make sure we remove dead nodes from the graph
|
2019-04-30 17:56:47 +00:00 |
|
fold-call-oper.ll
|
…
|
|
|
fold-call.ll
|
…
|
|
|
fold-imm.ll
|
…
|
|
|
fold-load-binops.ll
|
[X86] Add load folding isel patterns to scalar_math_patterns and AVX512_scalar_math_fp_patterns.
|
2019-06-11 04:30:53 +00:00 |
|
fold-load-unops.ll
|
[X86] Teach selectScalarSSELoad to not narrow volatile loads.
|
2019-06-27 05:51:56 +00:00 |
|
fold-load-vec.ll
|
…
|
|
|
fold-load.ll
|
…
|
|
|
fold-mul-lohi.ll
|
…
|
|
|
fold-pcmpeqd-1.ll
|
…
|
|
|
fold-pcmpeqd-2.ll
|
[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
|
2019-06-13 13:56:19 +00:00 |
|
fold-push.ll
|
…
|
|
|
fold-rmw-ops.ll
|
[X86] Teach isel for RMW binops to handle negate
|
2019-03-30 18:59:17 +00:00 |
|
fold-sext-trunc.ll
|
…
|
|
|
fold-tied-op.ll
|
Revert rL357745: [SelectionDAG] Compute known bits of CopyFromReg
|
2019-04-10 18:00:41 +00:00 |
|
fold-vector-bv-crash.ll
|
…
|
|
|
fold-vector-sext-crash.ll
|
…
|
|
|
fold-vector-sext-crash2.ll
|
…
|
|
|
fold-vector-sext-zext.ll
|
…
|
|
|
fold-vector-shl-crash.ll
|
…
|
|
|
fold-vector-shuffle-crash.ll
|
…
|
|
|
fold-vector-trunc-sitofp.ll
|
…
|
|
|
fold-vex.ll
|
…
|
|
|
fold-xmm-zero.ll
|
…
|
|
|
fold-zext-trunc.ll
|
…
|
|
|
fops-windows-itanium.ll
|
…
|
|
|
force-align-stack-alloca.ll
|
…
|
|
|
force-align-stack.ll
|
…
|
|
|
fp-arith.ll
|
…
|
|
|
fp-cvt.ll
|
[X86] Mark FP32_TO_INT16_IN_MEM/FP32_TO_INT32_IN_MEM/FP32_TO_INT64_IN_MEM as clobbering EFLAGS to prevent mis-scheduling during conversion from SelectionDAG to MIR.
|
2019-02-19 22:37:00 +00:00 |
|
fp-double-rounding.ll
|
…
|
|
|
fp-elim-and-no-fp-elim.ll
|
…
|
|
|
fp-elim.ll
|
…
|
|
|
fp-fast.ll
|
Move three folds for FADD, FSUB and FMUL in the DAG combiner away from Unsafe to more aligned checks that reflect context
|
2019-07-10 18:23:26 +00:00 |
|
fp-fold.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to fp-fast.ll fp-fold.ll fp-in-intregs.ll fp-stack-compare-cmov.ll fp-stack-compare.ll fsxor-alignment.ll"
|
2019-06-13 19:25:16 +00:00 |
|
fp-immediate-shorten.ll
|
…
|
|
|
fp-in-intregs.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to fp-fast.ll fp-fold.ll fp-in-intregs.ll fp-stack-compare-cmov.ll fp-stack-compare.ll fsxor-alignment.ll"
|
2019-06-13 19:25:16 +00:00 |
|
fp-intrinsics.ll
|
Add constrained fptrunc and fpext intrinsics.
|
2019-05-13 13:23:30 +00:00 |
|
fp-load-trunc.ll
|
…
|
|
|
fp-logic-replace.ll
|
…
|
|
|
fp-logic.ll
|
…
|
|
|
fp-select-cmp-and.ll
|
…
|
|
|
fp-stack-2results.ll
|
[NFC] This is a test for the commit access.
|
2019-05-06 08:31:18 +00:00 |
|
fp-stack-O0-crash.ll
|
…
|
|
|
fp-stack-O0.ll
|
…
|
|
|
fp-stack-compare-cmov.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to fp-fast.ll fp-fold.ll fp-in-intregs.ll fp-stack-compare-cmov.ll fp-stack-compare.ll fsxor-alignment.ll"
|
2019-06-13 19:25:16 +00:00 |
|
fp-stack-compare.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to fp-fast.ll fp-fold.ll fp-in-intregs.ll fp-stack-compare-cmov.ll fp-stack-compare.ll fsxor-alignment.ll"
|
2019-06-13 19:25:16 +00:00 |
|
fp-stack-direct-ret.ll
|
…
|
|
|
fp-stack-ret-conv.ll
|
…
|
|
|
fp-stack-ret-store.ll
|
…
|
|
|
fp-stack-ret.ll
|
…
|
|
|
fp-stack-retcopy.ll
|
…
|
|
|
fp-stack-set-st1.ll
|
…
|
|
|
fp-stack.ll
|
…
|
|
|
fp-trunc.ll
|
…
|
|
|
fp-undef.ll
|
…
|
|
|
fp-une-cmp.ll
|
…
|
|
|
fp2sint.ll
|
…
|
|
|
fp128-calling-conv.ll
|
…
|
|
|
fp128-cast.ll
|
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
|
2019-07-02 17:51:02 +00:00 |
|
fp128-compare.ll
|
…
|
|
|
fp128-extract.ll
|
…
|
|
|
fp128-g.ll
|
…
|
|
|
fp128-i128.ll
|
…
|
|
|
fp128-libcalls.ll
|
…
|
|
|
fp128-load.ll
|
…
|
|
|
fp128-select.ll
|
…
|
|
|
fp128-store.ll
|
…
|
|
|
fp_constant_op.ll
|
…
|
|
|
fp_load_cast_fold.ll
|
…
|
|
|
fp_load_fold.ll
|
…
|
|
|
fpcmp-soft-fp.ll
|
…
|
|
|
fpstack-debuginstr-kill.ll
|
…
|
|
|
fptosi-constant.ll
|
…
|
|
|
frame-base.ll
|
…
|
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|
frame-lowering-debug-intrinsic-2.ll
|
…
|
|
|
frame-lowering-debug-intrinsic.ll
|
…
|
|
|
frame-order.ll
|
…
|
|
|
frameaddr.ll
|
…
|
|
|
frameregister.ll
|
…
|
|
|
frem-msvc32.ll
|
…
|
|
|
fsgsbase.ll
|
…
|
|
|
fshl.ll
|
[X86] Promote i8 CMOV's (PR40965)
|
2019-03-15 21:17:53 +00:00 |
|
fshr.ll
|
[X86] Promote i8 CMOV's (PR40965)
|
2019-03-15 21:17:53 +00:00 |
|
fsxor-alignment.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to fp-fast.ll fp-fold.ll fp-in-intregs.ll fp-stack-compare-cmov.ll fp-stack-compare.ll fsxor-alignment.ll"
|
2019-06-13 19:25:16 +00:00 |
|
ftrunc.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
full-lsr.ll
|
…
|
|
|
funclet-layout.ll
|
…
|
|
|
function-alias.ll
|
…
|
|
|
function-subtarget-features-2.ll
|
…
|
|
|
function-subtarget-features.ll
|
…
|
|
|
funnel-shift-rot.ll
|
[X86] Fix the pattern changes from r356121 so that the ROR*r1/ROR*m1 pattern use the rotr opcode.
|
2019-03-14 16:53:24 +00:00 |
|
funnel-shift.ll
|
…
|
|
|
ga-offset.ll
|
…
|
|
|
ga-offset2.ll
|
…
|
|
|
gather-addresses.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
gcc_except_table.ll
|
…
|
|
|
gcc_except_table_functions.ll
|
…
|
|
|
gep-expanded-vector.ll
|
…
|
|
|
getelementptr.ll
|
…
|
|
|
gfni-intrinsics.ll
|
…
|
|
|
ghc-cc.ll
|
…
|
|
|
ghc-cc64.ll
|
…
|
|
|
global-access-pie-copyrelocs.ll
|
…
|
|
|
global-access-pie.ll
|
…
|
|
|
global-fill.ll
|
…
|
|
|
global-sections-comdat.ll
|
…
|
|
|
global-sections-tls.ll
|
…
|
|
|
global-sections.ll
|
…
|
|
|
gnu-seh-nolpads.ll
|
…
|
|
|
gpr-to-mask.ll
|
…
|
|
|
greedy_regalloc_bad_eviction_sequence.ll
|
…
|
|
|
gs-fold.ll
|
…
|
|
|
h-register-addressing-32.ll
|
…
|
|
|
h-register-addressing-64.ll
|
…
|
|
|
h-register-store.ll
|
…
|
|
|
h-registers-0.ll
|
…
|
|
|
h-registers-1.ll
|
…
|
|
|
h-registers-2.ll
|
…
|
|
|
h-registers-3.ll
|
…
|
|
|
haddsub-2.ll
|
…
|
|
|
haddsub-3.ll
|
[x86] make sure horizontal op and broadcast types match to simplify (PR41414)
|
2019-04-24 14:05:08 +00:00 |
|
haddsub-shuf.ll
|
[X86][AVX] Add broadcast(v4f64 hadd) test
|
2019-06-13 11:42:32 +00:00 |
|
haddsub-undef.ll
|
[X86][SSE] Relax use limits for lowerAddSubToHorizontalOp (PR32433)
|
2019-05-13 16:02:45 +00:00 |
|
haddsub.ll
|
Change semantics of fadd/fmul vector reductions.
|
2019-06-11 08:22:10 +00:00 |
|
half.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
handle-move.ll
|
…
|
|
|
hhvm-cc.ll
|
…
|
|
|
hidden-vis-2.ll
|
…
|
|
|
hidden-vis-3.ll
|
…
|
|
|
hidden-vis-4.ll
|
…
|
|
|
hidden-vis-pic.ll
|
…
|
|
|
hidden-vis.ll
|
…
|
|
|
hipe-cc.ll
|
…
|
|
|
hipe-cc64.ll
|
…
|
|
|
hipe-prologue.ll
|
…
|
|
|
hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
|
[NFC][Codegen][X86] Add AVX2 runline for '(X & (C l>> Y)) ==/!= 0' tests
|
2019-06-05 14:08:11 +00:00 |
|
hoist-and-by-const-from-shl-in-eqcmp-zero.ll
|
[NFC][Codegen][X86] Add AVX2 runline for '(X & (C l>> Y)) ==/!= 0' tests
|
2019-06-05 14:08:11 +00:00 |
|
hoist-common.ll
|
…
|
|
|
hoist-invariant-load.ll
|
Allow unordered loads to be considered invariant in CodeGen
|
2019-03-19 18:27:18 +00:00 |
|
hoist-spill-lpad.ll
|
…
|
|
|
hoist-spill.ll
|
[X86] Remove icmp undef from reduced tests
|
2019-03-24 17:02:08 +00:00 |
|
horizontal-reduce-smax.ll
|
[X86][SSE] X86TargetLowering::isBinOp - add PCMPGT
|
2019-06-26 14:34:41 +00:00 |
|
horizontal-reduce-smin.ll
|
[X86][SSE] X86TargetLowering::isBinOp - add PCMPGT
|
2019-06-26 14:34:41 +00:00 |
|
horizontal-reduce-umax.ll
|
[X86][SSE] X86TargetLowering::isBinOp - add PCMPGT
|
2019-06-26 14:34:41 +00:00 |
|
horizontal-reduce-umin.ll
|
[X86][SSE] X86TargetLowering::isBinOp - add PCMPGT
|
2019-06-26 14:34:41 +00:00 |
|
horizontal-shuffle-demanded.ll
|
[X86][SSE] SimplifyDemandedBits - call PEXTRB/PEXTRW SimplifyDemandedVectorElts as well.
|
2019-05-11 21:35:50 +00:00 |
|
horizontal-shuffle.ll
|
…
|
|
|
huge-stack-offset.ll
|
…
|
|
|
huge-stack-offset2.ll
|
…
|
|
|
i1narrowfail.ll
|
…
|
|
|
i2k.ll
|
…
|
|
|
i16lshr8pat.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
i64-mem-copy.ll
|
[X86][AVX] EltsFromConsecutiveLoads - Add BROADCAST lowering support
|
2019-02-19 15:57:09 +00:00 |
|
i64-to-float.ll
|
[X86][AVX] X86ISD::PERMV/PERMV3 node types can never fold index ops
|
2019-04-16 19:18:53 +00:00 |
|
i128-add.ll
|
[X86] getTargetConstantBitsFromNode - remove unnecessary getZExtValue() (PR42486)
|
2019-07-02 18:20:38 +00:00 |
|
i128-and-beyond.ll
|
…
|
|
|
i128-immediate.ll
|
…
|
|
|
i128-mul.ll
|
…
|
|
|
i128-ret.ll
|
…
|
|
|
i128-sdiv.ll
|
…
|
|
|
i256-add.ll
|
…
|
|
|
i386-setjmp-pic.ll
|
…
|
|
|
i386-shrink-wrapping.ll
|
[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
|
2019-06-13 13:56:19 +00:00 |
|
i386-tlscall-fastregalloc.ll
|
…
|
|
|
i486-fence-loop.ll
|
…
|
|
|
i686-win-shrink-wrapping.ll
|
…
|
|
|
iabs.ll
|
[X86] Promote i16 SRA instructions to i32
|
2019-04-05 06:32:50 +00:00 |
|
icall-branch-funnel.ll
|
[CodeGen] Make branch funnels pass the machine verifier
|
2019-07-03 17:16:45 +00:00 |
|
icmp-opt.ll
|
…
|
|
|
ident-metadata.ll
|
…
|
|
|
ifunc-asm.ll
|
…
|
|
|
illegal-bitfield-loadstore.ll
|
…
|
|
|
illegal-insert.ll
|
…
|
|
|
illegal-vector-args-return.ll
|
…
|
|
|
immediate_merging.ll
|
Revert r356688 "[X86] Don't avoid folding multiple use sign extended 8-bit immediate into instructions under optsize."
|
2019-03-25 01:25:32 +00:00 |
|
immediate_merging64.ll
|
Revert r356688 "[X86] Don't avoid folding multiple use sign extended 8-bit immediate into instructions under optsize."
|
2019-03-25 01:25:32 +00:00 |
|
implicit-faultmap.ll
|
For faulting ops, include a comment w/the fault destination
|
2019-03-12 21:05:31 +00:00 |
|
implicit-null-check-negative.ll
|
…
|
|
|
implicit-null-check.ll
|
[ImplicitNullChecks] Support unordered atomic accesses
|
2019-03-13 03:25:20 +00:00 |
|
implicit-null-checks.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
implicit-null-chk-reg-rewrite.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
implicit-use-spill.mir
|
…
|
|
|
imul-lea-2.ll
|
…
|
|
|
imul-lea.ll
|
…
|
|
|
imul.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
inalloca-ctor.ll
|
…
|
|
|
inalloca-invoke.ll
|
…
|
|
|
inalloca-regparm.ll
|
…
|
|
|
inalloca-stdcall.ll
|
…
|
|
|
inalloca.ll
|
…
|
|
|
inc-of-add.ll
|
[NFC][Codegen][X86][AArch64][ARM][PowerPC] Recommit: Add test coverage for "add-of-inc" vs "sub-of-not"
|
2019-07-02 16:48:49 +00:00 |
|
inconsistent_landingpad.ll
|
…
|
|
|
indirect-branch-tracking-r2.ll
|
[X86] [CET] Deal with return-twice function such as vfork, setjmp when
|
2019-05-22 00:50:21 +00:00 |
|
indirect-branch-tracking.ll
|
…
|
|
|
indirect-hidden.ll
|
…
|
|
|
init-priority.ll
|
[IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format
|
2019-05-15 02:35:32 +00:00 |
|
inline-0bh.ll
|
…
|
|
|
inline-asm-2addr.ll
|
…
|
|
|
inline-asm-A-constraint.ll
|
…
|
|
|
inline-asm-R-constraint.ll
|
…
|
|
|
inline-asm-avx-v-constraint-32bit.ll
|
…
|
|
|
inline-asm-avx-v-constraint.ll
|
…
|
|
|
inline-asm-avx512f-v-constraint.ll
|
…
|
|
|
inline-asm-avx512f-x-constraint.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
inline-asm-avx512vl-v-constraint-32bit.ll
|
…
|
|
|
inline-asm-avx512vl-v-constraint.ll
|
…
|
|
|
inline-asm-bad-constraint-n.ll
|
…
|
|
|
inline-asm-bad-modifier.ll
|
…
|
|
|
inline-asm-default-clobbers.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
inline-asm-duplicated-constraint.ll
|
…
|
|
|
inline-asm-error.ll
|
…
|
|
|
inline-asm-flag-clobber.ll
|
…
|
|
|
inline-asm-flag-output.ll
|
[X86] Fix copy-paste error in @ccz flag.
|
2019-02-21 15:28:31 +00:00 |
|
inline-asm-fpstack.ll
|
[X86] Don't set exception mask bits when modifying FPCW to change rounding mode for fp->int conversion
|
2019-02-15 21:59:33 +00:00 |
|
inline-asm-h.ll
|
…
|
|
|
inline-asm-i-constraint-i1.ll
|
[X86] Extend boolean arguments to inline-asm according to getBooleanType
|
2019-04-03 17:43:14 +00:00 |
|
inline-asm-modifier-V.ll
|
…
|
|
|
inline-asm-modifier-c.ll
|
[AsmPrinter] refactor to support %c w/ GlobalAddress'
|
2019-04-26 18:45:04 +00:00 |
|
inline-asm-modifier-n.ll
|
…
|
|
|
inline-asm-modifier-q.ll
|
…
|
|
|
inline-asm-mrv.ll
|
…
|
|
|
inline-asm-multilevel-gep.ll
|
[TargetLowering] Handle multi depth GEPs w/ inline asm constraints
|
2019-05-13 17:27:44 +00:00 |
|
inline-asm-out-regs.ll
|
…
|
|
|
inline-asm-pic.ll
|
…
|
|
|
inline-asm-ptr-cast.ll
|
…
|
|
|
inline-asm-q-regs.ll
|
…
|
|
|
inline-asm-sp-clobber-memcpy.ll
|
…
|
|
|
inline-asm-stack-realign.ll
|
…
|
|
|
inline-asm-stack-realign2.ll
|
…
|
|
|
inline-asm-stack-realign3.ll
|
…
|
|
|
inline-asm-tied.ll
|
…
|
|
|
inline-asm-x-scalar.ll
|
…
|
|
|
inline-asm.ll
|
…
|
|
|
inline-sse.ll
|
…
|
|
|
inlineasm-sched-bug.ll
|
…
|
|
|
inreg.ll
|
…
|
|
|
ins_split_regalloc.ll
|
…
|
|
|
ins_subreg_coalesce-1.ll
|
…
|
|
|
ins_subreg_coalesce-2.ll
|
…
|
|
|
ins_subreg_coalesce-3.ll
|
…
|
|
|
insert-into-constant-vector.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
insert-loaded-scalar.ll
|
…
|
|
|
insert-positions.ll
|
…
|
|
|
insert-prefetch-inline.afdo
|
…
|
|
|
insert-prefetch-inline.ll
|
…
|
|
|
insert-prefetch-invalid-instr.afdo
|
…
|
|
|
insert-prefetch-invalid-instr.ll
|
…
|
|
|
insert-prefetch-other.afdo
|
…
|
|
|
insert-prefetch.afdo
|
…
|
|
|
insert-prefetch.ll
|
…
|
|
|
insertelement-copytoregs.ll
|
…
|
|
|
insertelement-duplicates.ll
|
…
|
|
|
insertelement-legalize.ll
|
…
|
|
|
insertelement-ones.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
insertelement-shuffle.ll
|
[X86][AVX] Update VBROADCAST folds to always use v2i64 X86vzload
|
2019-02-19 16:33:17 +00:00 |
|
insertelement-var-index.ll
|
…
|
|
|
insertelement-zero.ll
|
[X86][AVX] Split VZEXT_MOVL ymm/zmm if the upper elements are not demanded.
|
2019-05-12 15:16:29 +00:00 |
|
insertps-O0-bug.ll
|
…
|
|
|
insertps-combine.ll
|
…
|
|
|
insertps-from-constantpool.ll
|
…
|
|
|
insertps-unfold-load-bug.ll
|
…
|
|
|
instr-symbols.mir
|
…
|
|
|
int-intrinsic.ll
|
…
|
|
|
intersect-fma-fmf.ll
|
…
|
|
|
interval-update-remat.ll
|
…
|
|
|
invalid-liveness.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
invalid-shift-immediate.ll
|
…
|
|
|
invpcid-intrinsic.ll
|
…
|
|
|
ipra-inline-asm.ll
|
RegUsageInfoCollector: Skip AMDGPU entry point functions
|
2019-07-05 23:33:43 +00:00 |
|
ipra-local-linkage.ll
|
…
|
|
|
ipra-reg-alias.ll
|
…
|
|
|
ipra-reg-usage.ll
|
RegUsageInfoCollector: Skip AMDGPU entry point functions
|
2019-07-05 23:33:43 +00:00 |
|
ipra-transform.ll
|
…
|
|
|
is-constant.ll
|
…
|
|
|
isel-optnone.ll
|
…
|
|
|
isel-sink.ll
|
…
|
|
|
isel-sink2.ll
|
…
|
|
|
isel-sink3.ll
|
…
|
|
|
isint.ll
|
…
|
|
|
isnan.ll
|
…
|
|
|
isnan2.ll
|
…
|
|
|
ispositive.ll
|
…
|
|
|
jump_sign.ll
|
[X86] Merge negated ISD::SUB nodes into X86ISD::SUB equivalent (PR40483)
|
2019-07-11 15:56:33 +00:00 |
|
known-bits-vector.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
known-bits.ll
|
…
|
|
|
known-signbits-vector.ll
|
[TargetLowering] SimplifyDemandedVectorElts - add shift/rotate support.
|
2019-06-27 14:25:54 +00:00 |
|
kshift.ll
|
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ
|
2019-06-26 14:40:49 +00:00 |
|
label-annotation.ll
|
[codeview] Fix SDNode representation of annotation labels
|
2019-05-15 21:46:05 +00:00 |
|
label-heapallocsite.ll
|
Fix bug in getCompleteTypeIndex in codeview debug info
|
2019-05-06 23:37:03 +00:00 |
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label-redefinition.ll
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…
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lack-of-signed-truncation-check.ll
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[X86] Suppress load folding for add/sub with 128 immediate.
|
2019-03-06 07:36:36 +00:00 |
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lakemont.ll
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…
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large-code-model-isel.ll
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…
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large-constants.ll
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…
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large-gep-chain.ll
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…
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large-gep-scale.ll
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…
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large-global.ll
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…
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large-pic-string.ll
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…
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late-address-taken.ll
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…
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late-remat-update-2.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
late-remat-update.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
ldzero.ll
|
…
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lea-2.ll
|
[x86] update test checks; NFC
|
2019-04-15 17:38:47 +00:00 |
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lea-3.ll
|
[x86] update test checks; NFC
|
2019-04-15 17:38:47 +00:00 |
|
lea-4.ll
|
[x86] update test checks; NFC
|
2019-04-15 17:38:47 +00:00 |
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lea-5.ll
|
…
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lea-dagdag.ll
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[x86] try to widen 'shl' as part of LEA formation
|
2019-04-17 22:38:51 +00:00 |
|
lea-opt-cse1.ll
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…
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lea-opt-cse2.ll
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…
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lea-opt-cse3.ll
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…
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lea-opt-cse4.ll
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…
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lea-opt-memop-check-1.ll
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…
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lea-opt-memop-check-2.ll
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…
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lea-opt-with-debug.mir
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…
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lea-opt.ll
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…
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lea-recursion.ll
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…
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lea.ll
|
[X86] Regenerate LEA codegen tests
|
2019-04-03 12:33:16 +00:00 |
|
leaFixup32.mir
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
leaFixup64.mir
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
leaf-fp-elim.ll
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…
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legalize-fmp-oeq-vector-select.ll
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…
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legalize-libcalls.ll
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…
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legalize-shift-64.ll
|
[DAGCombine] Prune unnused nodes.
|
2019-03-29 17:35:56 +00:00 |
|
legalize-shift.ll
|
…
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legalize-shl-vec.ll
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…
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legalize-sub-zero-2.ll
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…
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legalize-sub-zero.ll
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…
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legalize-types-remapid.ll
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…
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legalize-vaarg.ll
|
[SelectionDAG] Legalize vaargs that require vector splitting
|
2019-06-18 12:24:02 +00:00 |
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legalizedag_vec.ll
|
…
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libcall-sret.ll
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…
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licm-dominance.ll
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…
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licm-nested.ll
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…
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licm-regpressure.ll
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…
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licm-symbol.ll
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…
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lifetime-alias.ll
|
[DAGCombiner] Fix invalid alias analysis.
|
2019-05-13 09:07:37 +00:00 |
|
limit-split-cost.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
limited-prec.ll
|
…
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linux-preemption.ll
|
…
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lit.local.cfg
|
[lit] Delete empty lines at the end of lit.local.cfg NFC
|
2019-06-17 09:51:07 +00:00 |
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live-out-reg-info.ll
|
…
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live-range-nosubreg.ll
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…
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liveness-local-regalloc.ll
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…
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llc-override-mcpu-mattr.ll
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…
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llc-print-machineinstrs.mir
|
…
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llc-start-stop-instance.ll
|
…
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llrint-conv-i32.ll
|
[CodeGen] Add lrint/llrint builtins
|
2019-05-28 20:47:44 +00:00 |
|
llrint-conv.ll
|
[CodeGen] Add lrint/llrint builtins
|
2019-05-28 20:47:44 +00:00 |
|
llround-conv-i32.ll
|
[CodeGen] Add lround/llround builtins
|
2019-05-16 13:15:27 +00:00 |
|
llround-conv.ll
|
[CodeGen] Add lround/llround builtins
|
2019-05-16 13:15:27 +00:00 |
|
load-combine-dbg.ll
|
…
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load-combine.ll
|
[DAG] Refactor DAGCombiner::ReassociateOps
|
2019-04-29 17:50:10 +00:00 |
|
load-local-v3i1.ll
|
[LegalizeVectorTypes] Allow single loads and stores for more short vectors
|
2019-03-27 20:35:56 +00:00 |
|
load-partial.ll
|
[X86][SSE] EltsFromConsecutiveLoads - add basic dereferenceable support
|
2019-07-10 10:46:36 +00:00 |
|
load-scalar-as-vector.ll
|
[X86] Promote i16 SRA instructions to i32
|
2019-04-05 06:32:50 +00:00 |
|
load-slice.ll
|
…
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loadStore_vectorizer.ll
|
…
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loc-remat.ll
|
…
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local_stack_symbol_ordering.ll
|
…
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localescape.ll
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…
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log2_not_readnone.ll
|
…
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logical-load-fold.ll
|
…
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long-setcc.ll
|
…
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|
longlong-deadload.ll
|
…
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|
loop-blocks.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
loop-hoist.ll
|
…
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|
|
loop-rotate.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
loop-search.ll
|
[Codegen] Merge tail blocks with no successors after block placement
|
2019-06-13 18:11:32 +00:00 |
|
loop-strength-reduce-2.ll
|
…
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loop-strength-reduce-3.ll
|
…
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loop-strength-reduce-crash.ll
|
…
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loop-strength-reduce.ll
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…
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loop-strength-reduce2.ll
|
…
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loop-strength-reduce4.ll
|
…
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loop-strength-reduce5.ll
|
…
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loop-strength-reduce6.ll
|
…
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loop-strength-reduce7.ll
|
…
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loop-strength-reduce8.ll
|
…
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|
lower-bitcast.ll
|
…
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|
lower-vec-shift-2.ll
|
…
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|
lower-vec-shift.ll
|
[X86] Prefer VPBLENDD for v2i64/v4i64 blends with AVX2.
|
2019-03-03 00:18:07 +00:00 |
|
lower-vec-shuffle-bug.ll
|
…
|
|
|
lrint-conv-i32.ll
|
[CodeGen] Add lrint/llrint builtins
|
2019-05-28 20:47:44 +00:00 |
|
lrint-conv.ll
|
[CodeGen] Add lrint/llrint builtins
|
2019-05-28 20:47:44 +00:00 |
|
lround-conv-i32.ll
|
[CodeGen] Add lround/llround builtins
|
2019-05-16 13:15:27 +00:00 |
|
lround-conv.ll
|
[CodeGen] Add lround/llround builtins
|
2019-05-16 13:15:27 +00:00 |
|
lrshrink.ll
|
…
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|
lsr-crash-empty-uses.ll
|
…
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|
lsr-delayed-fold.ll
|
…
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lsr-i386.ll
|
…
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|
lsr-interesting-step.ll
|
…
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|
lsr-loop-exit-cond.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
lsr-negative-stride.ll
|
…
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|
|
lsr-nonaffine.ll
|
…
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|
lsr-normalization.ll
|
…
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|
lsr-overflow.ll
|
…
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|
lsr-quadratic-expand.ll
|
…
|
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|
lsr-redundant-addressing.ll
|
…
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|
|
lsr-reuse-trunc.ll
|
…
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|
|
lsr-reuse.ll
|
…
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|
|
lsr-sort.ll
|
…
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|
lsr-static-addr.ll
|
[X86] Initial cleanups on the FixupLEAs pass. Separate Atom LEA creation from other LEA optimizations.
|
2019-04-30 17:56:28 +00:00 |
|
lsr-wrap.ll
|
…
|
|
|
lwp-intrinsics-x86_64.ll
|
…
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|
|
lwp-intrinsics.ll
|
[X86] Add a non-ambiguous check prefix to lwp-intrinsics.ll for the case when only the feature is specified and not the CPUs.
|
2019-05-08 19:20:53 +00:00 |
|
lzcnt-tzcnt.ll
|
…
|
|
|
lzcnt-zext-cmp.ll
|
[X86] AMD znver2 enablement
|
2019-02-26 16:55:10 +00:00 |
|
lzcnt.ll
|
[X86] Regenerate LZCNT tests on x86/x32/x64 targets
|
2019-05-23 13:30:10 +00:00 |
|
macCatalyst.ll
|
[macCatalyst] Use macCatalyst pretty name in .build_version darwin
|
2019-07-12 22:06:08 +00:00 |
|
machine-combiner-int-vec.ll
|
[DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support
|
2019-07-11 14:45:03 +00:00 |
|
machine-combiner-int.ll
|
…
|
|
|
machine-combiner.ll
|
[X86] Add avx512 command lines and test cases to machine-combiner.ll
|
2019-06-02 00:07:48 +00:00 |
|
machine-copy-prop.mir
|
…
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|
|
machine-cp-debug.mir
|
…
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|
|
machine-cp.ll
|
[Codegen] Merge tail blocks with no successors after block placement
|
2019-06-13 18:11:32 +00:00 |
|
machine-cse.ll
|
…
|
|
|
machine-outliner-debuginfo.ll
|
…
|
|
|
machine-outliner-disubprogram.ll
|
…
|
|
|
machine-outliner-noredzone.ll
|
…
|
|
|
machine-outliner-tailcalls.ll
|
…
|
|
|
machine-outliner.ll
|
…
|
|
|
machine-region-info.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
machine-sink-and-implicit-null-checks.ll
|
…
|
|
|
machine-sink.ll
|
…
|
|
|
machine-trace-metrics-crash.ll
|
[X86] Avoid icmp undef in reduced tests
|
2019-03-13 18:36:59 +00:00 |
|
machinesink-merge-debuginfo.ll
|
[debug-info] Make a couple of tests more robust.
|
2019-06-27 15:53:07 +00:00 |
|
machinesink-null-debuginfo.ll
|
[debug-info] Make a couple of tests more robust.
|
2019-06-27 15:53:07 +00:00 |
|
macho-comdat.ll
|
…
|
|
|
macho-trap.ll
|
…
|
|
|
madd.ll
|
[DAGCombiner] try to move bitcast after extract_subvector
|
2019-05-12 14:43:20 +00:00 |
|
mangle-question-mark.ll
|
…
|
|
|
mask-negated-bool.ll
|
…
|
|
|
masked-iv-safe.ll
|
…
|
|
|
masked-iv-unsafe.ll
|
…
|
|
|
masked_compressstore.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
masked_expandload.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
masked_gather.ll
|
[MIR] Add simple PRE pass to MachineCSE
|
2019-06-09 12:15:47 +00:00 |
|
masked_gather_scatter.ll
|
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
|
2019-06-25 10:51:15 +00:00 |
|
masked_gather_scatter_widen.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
masked_load.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
masked_store.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
masked_store_trunc.ll
|
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ
|
2019-06-26 14:40:49 +00:00 |
|
masked_store_trunc_ssat.ll
|
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ
|
2019-06-26 14:40:49 +00:00 |
|
masked_store_trunc_usat.ll
|
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ
|
2019-06-26 14:40:49 +00:00 |
|
maskmovdqu.ll
|
…
|
|
|
materialize.ll
|
…
|
|
|
mature-mc-support.ll
|
…
|
|
|
mbp-false-cfg-break.ll
|
…
|
|
|
mcinst-avx-lowering.ll
|
…
|
|
|
mcinst-lowering.ll
|
…
|
|
|
mcu-abi.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
mem-intrin-base-reg.ll
|
…
|
|
|
mem-promote-integers.ll
|
…
|
|
|
membarrier.ll
|
…
|
|
|
memcmp-mergeexpand.ll
|
Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."
|
2019-06-26 12:13:13 +00:00 |
|
memcmp-minsize.ll
|
…
|
|
|
memcmp-optsize.ll
|
Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."
|
2019-06-26 12:13:13 +00:00 |
|
memcmp.ll
|
Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."
|
2019-06-26 12:13:13 +00:00 |
|
memcpy-2.ll
|
…
|
|
|
memcpy-from-string.ll
|
…
|
|
|
memcpy-struct-by-value.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
memcpy.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
mempcpy-32.ll
|
…
|
|
|
mempcpy.ll
|
…
|
|
|
memset-2.ll
|
…
|
|
|
memset-3.ll
|
…
|
|
|
memset-nonzero.ll
|
[x86] split more 256-bit stores of concatenated vectors
|
2019-06-05 16:40:57 +00:00 |
|
memset-sse-stack-realignment.ll
|
…
|
|
|
memset-zero.ll
|
[Tests] Expand coverage of small memset zero idioms
|
2019-05-07 23:48:42 +00:00 |
|
memset.ll
|
…
|
|
|
memset64-on-x86-32.ll
|
…
|
|
|
merge-consecutive-loads-128.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
|
merge-consecutive-loads-256.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
|
merge-consecutive-loads-512.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
|
merge-consecutive-stores-i1.ll
|
…
|
|
|
merge-consecutive-stores-nt.ll
|
[X86][AMDGPU][DAGCombiner] Move call to allowsMemoryAccess into isLoadBitCastBeneficial/isStoreBitCastBeneficial to allow X86 to bypass it
|
2019-07-09 19:55:28 +00:00 |
|
merge-consecutive-stores.ll
|
…
|
|
|
merge-sp-update-lea.ll
|
…
|
|
|
merge-sp-updates-cfi.ll
|
…
|
|
|
merge-store-constants.ll
|
…
|
|
|
merge-store-partially-alias-loads.ll
|
…
|
|
|
merge-vector-stores-scale-idx-crash.ll
|
…
|
|
|
merge_store.ll
|
[DAG] Refactor DAGCombiner::ReassociateOps
|
2019-04-29 17:50:10 +00:00 |
|
merge_store_duplicated_loads.ll
|
…
|
|
|
mfence.ll
|
…
|
|
|
midpoint-int-vec-128.ll
|
Revert r356996 "[DAG] Avoid smart constructor-based dangling nodes."
|
2019-03-27 19:54:41 +00:00 |
|
midpoint-int-vec-256.ll
|
[x86] narrow extract subvector of vector select
|
2019-06-07 13:17:46 +00:00 |
|
midpoint-int-vec-512.ll
|
[NFC][CodeGen][X86][AArch64] Add tests for C++ std::midpoint() pattern (PR40965)
|
2019-03-05 20:18:47 +00:00 |
|
midpoint-int.ll
|
[X86] Promote i8 CMOV's (PR40965)
|
2019-03-15 21:17:53 +00:00 |
|
min-legal-vector-width.ll
|
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
|
2019-03-13 17:07:09 +00:00 |
|
mingw-alloca.ll
|
…
|
|
|
mingw-comdats-xdata.ll
|
…
|
|
|
mingw-comdats.ll
|
…
|
|
|
mingw-refptr.ll
|
…
|
|
|
misaligned-memset.ll
|
…
|
|
|
misched-aa-colored.ll
|
…
|
|
|
misched-aa-mmos.ll
|
…
|
|
|
misched-balance.ll
|
…
|
|
|
misched-code-difference-with-debug.ll
|
…
|
|
|
misched-copy.ll
|
…
|
|
|
misched-crash.ll
|
…
|
|
|
misched-fusion.ll
|
…
|
|
|
misched-ilp.ll
|
…
|
|
|
misched-matmul.ll
|
…
|
|
|
misched-matrix.ll
|
…
|
|
|
misched-new.ll
|
…
|
|
|
misched_phys_reg_assign_order.ll
|
Recommit r358211 "[X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87, but no SSE2"
|
2019-04-11 19:19:42 +00:00 |
|
mmx-arg-passing-x86-64.ll
|
…
|
|
|
mmx-arg-passing.ll
|
…
|
|
|
mmx-arith.ll
|
…
|
|
|
mmx-bitcast-fold.ll
|
…
|
|
|
mmx-bitcast.ll
|
…
|
|
|
mmx-build-vector.ll
|
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
|
2019-07-02 17:51:02 +00:00 |
|
mmx-coalescing.ll
|
…
|
|
|
mmx-copy-gprs.ll
|
…
|
|
|
mmx-cvt.ll
|
…
|
|
|
mmx-fold-load.ll
|
…
|
|
|
mmx-fold-zero.ll
|
…
|
|
|
mmx-intrinsics.ll
|
…
|
|
|
mmx-only.ll
|
…
|
|
|
mod128.ll
|
…
|
|
|
movbe.ll
|
…
|
|
|
movddup-load-fold.ll
|
…
|
|
|
movdir-intrinsic-x86.ll
|
…
|
|
|
movdir-intrinsic-x86_64.ll
|
…
|
|
|
move_latch_to_loop_top.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
movfs.ll
|
…
|
|
|
movgs.ll
|
…
|
|
|
movmsk-cmp.ll
|
[X86][AVX] truncateVectorWithPACK - avoid bitcasted shuffles
|
2019-06-26 09:50:11 +00:00 |
|
movmsk.ll
|
[DAGCombine] Prune unnused nodes.
|
2019-03-29 17:35:56 +00:00 |
|
movntdq-no-avx.ll
|
…
|
|
|
movpc32-check.ll
|
…
|
|
|
movtopush.ll
|
…
|
|
|
movtopush.mir
|
Describe stack-id as an enum
|
2019-06-17 09:13:29 +00:00 |
|
movtopush64.ll
|
…
|
|
|
ms-inline-asm-avx512.ll
|
…
|
|
|
ms-inline-asm-redundant-clobber.ll
|
…
|
|
|
ms-inline-asm.ll
|
…
|
|
|
mul-constant-i8.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
mul-constant-i16.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
mul-constant-i32.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
mul-constant-i64.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
mul-constant-result.ll
|
[Codegen] Merge tail blocks with no successors after block placement
|
2019-06-13 18:11:32 +00:00 |
|
mul-i256.ll
|
…
|
|
|
mul-i512.ll
|
…
|
|
|
mul-i1024.ll
|
…
|
|
|
mul-legalize.ll
|
…
|
|
|
mul-remat.ll
|
…
|
|
|
mul-shift-reassoc.ll
|
…
|
|
|
mul64.ll
|
…
|
|
|
mul128.ll
|
[X86] Add PR13897 test case (i128 mul on i686)
|
2019-03-22 17:52:21 +00:00 |
|
mul128_sext_loop.ll
|
…
|
|
|
mulo-pow2.ll
|
[SDAG] Recursively legalize both vector mulo results
|
2019-05-10 20:42:48 +00:00 |
|
muloti.ll
|
…
|
|
|
mult-alt-generic-i686.ll
|
…
|
|
|
mult-alt-generic-x86_64.ll
|
…
|
|
|
mult-alt-x86.ll
|
…
|
|
|
multiple-loop-post-inc.ll
|
…
|
|
|
multiple-return-values-cross-block.ll
|
…
|
|
|
mulvi32.ll
|
[DAGCombiner] narrow shuffle of concatenated vectors
|
2019-04-12 16:31:56 +00:00 |
|
mulx32.ll
|
…
|
|
|
mulx64.ll
|
…
|
|
|
musttail-fastcall.ll
|
…
|
|
|
musttail-indirect.ll
|
…
|
|
|
musttail-thiscall.ll
|
…
|
|
|
musttail-varargs.ll
|
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
|
2019-03-13 17:07:09 +00:00 |
|
musttail.ll
|
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
|
2019-03-13 17:07:09 +00:00 |
|
mwaitx.ll
|
[X86] Remove CustomInserter pseudos for MONITOR/MONITORX/CLZERO. Use custom instruction selection instead.
|
2019-04-03 23:28:30 +00:00 |
|
named-reg-alloc.ll
|
…
|
|
|
named-reg-notareg.ll
|
…
|
|
|
nancvt.ll
|
…
|
|
|
narrow-shl-cst.ll
|
[X86] Don't turn (and (shl X, C1), C2) into (shl (and X, (C1 >> C2), C2) if the original AND can represented by MOVZX.
|
2019-04-20 04:38:53 +00:00 |
|
narrow-shl-load.ll
|
…
|
|
|
narrow_op-1.ll
|
…
|
|
|
neg-of-3ops-lea.ll
|
[X86][Codegen] Add missed pattern that may be a lea+neg
|
2019-06-08 19:38:14 +00:00 |
|
neg-shl-add.ll
|
…
|
|
|
neg_cmp.ll
|
…
|
|
|
neg_fp.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to some X86/ and XCore/ tests."
|
2019-06-13 19:24:51 +00:00 |
|
negate-add-zero.ll
|
[IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format
|
2019-05-15 02:35:32 +00:00 |
|
negate-i1.ll
|
…
|
|
|
negate-shift.ll
|
…
|
|
|
negate.ll
|
…
|
|
|
negative-offset.ll
|
[NFC][X86] Autogenerate negative-offset.ll test
|
2019-05-22 15:34:43 +00:00 |
|
negative-sin.ll
|
…
|
|
|
negative-stride-fptosi-user.ll
|
…
|
|
|
negative-subscript.ll
|
…
|
|
|
negative_zero.ll
|
…
|
|
|
new-remat.ll
|
…
|
|
|
newline-and-quote.ll
|
…
|
|
|
no-and8ri8.ll
|
…
|
|
|
no-cmov.ll
|
…
|
|
|
no-plt-libcalls.ll
|
Add, and infer, a nofree function attribute
|
2019-07-08 15:57:56 +00:00 |
|
no-plt.ll
|
…
|
|
|
no-prolog-kill.ll
|
…
|
|
|
no-sse2-avg.ll
|
…
|
|
|
no-stack-arg-probe.ll
|
…
|
|
|
nobt.ll
|
…
|
|
|
nocf_check.ll
|
…
|
|
|
nocx16.ll
|
…
|
|
|
non-lazy-bind.ll
|
…
|
|
|
non-unique-sections.ll
|
…
|
|
|
non-value-mem-operand.mir
|
[X86] Introduce new MOVSSrm/MOVSDrm opcodes that use VR128 register class.
|
2019-06-18 03:23:11 +00:00 |
|
nonconst-static-ev.ll
|
…
|
|
|
nonconst-static-iv.ll
|
…
|
|
|
nontemporal-2.ll
|
[DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support
|
2019-07-11 14:45:03 +00:00 |
|
nontemporal-3.ll
|
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026)
|
2019-06-17 18:20:04 +00:00 |
|
nontemporal-loads-2.ll
|
[X86][SSE] Add tests for underaligned nt loads
|
2019-06-17 14:38:17 +00:00 |
|
nontemporal-loads.ll
|
[X86][SSE] VSELECT(XOR(Cond,-1), LHS, RHS) --> VSELECT(Cond, RHS, LHS)
|
2019-03-06 10:54:43 +00:00 |
|
nontemporal.ll
|
…
|
|
|
noreturn-call.ll
|
…
|
|
|
norex-subreg.ll
|
…
|
|
|
nosse-error1.ll
|
…
|
|
|
nosse-error2.ll
|
…
|
|
|
nosse-varargs.ll
|
…
|
|
|
nosse-vector.ll
|
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
|
2019-03-13 17:07:09 +00:00 |
|
not-and-simplify.ll
|
[DAGCombine] Prune unnused nodes.
|
2019-03-29 17:35:56 +00:00 |
|
note-cet-property.ll
|
…
|
|
|
note-sections.ll
|
…
|
|
|
null-streamer.ll
|
…
|
|
|
objc-gc-module-flags.ll
|
…
|
|
|
object-size.ll
|
…
|
|
|
oddshuffles.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
|
oddsubvector.ll
|
[x86] split 256-bit store of concatenated vectors
|
2019-06-04 16:40:04 +00:00 |
|
omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
|
[CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 3)
|
2019-06-27 21:52:10 +00:00 |
|
opaque-constant-asm.ll
|
…
|
|
|
opt-ext-uses.ll
|
…
|
|
|
opt-shuff-tstore.ll
|
…
|
|
|
opt_phis.mir
|
…
|
|
|
opt_phis2.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
optimize-max-0.ll
|
…
|
|
|
optimize-max-1.ll
|
…
|
|
|
optimize-max-2.ll
|
…
|
|
|
optimize-max-3.ll
|
…
|
|
|
or-address.ll
|
…
|
|
|
or-branch.ll
|
[Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr)
|
2019-06-25 17:29:18 +00:00 |
|
or-lea.ll
|
…
|
|
|
osx-private-labels.ll
|
…
|
|
|
overflow-intrinsic-setcc-fold.ll
|
…
|
|
|
overflow.ll
|
…
|
|
|
overlap-shift.ll
|
…
|
|
|
packed_struct.ll
|
…
|
|
|
packss.ll
|
[X86][SSE] Regenerated packss.ll test file.
|
2019-07-15 16:23:42 +00:00 |
|
paddus.ll
|
…
|
|
|
palignr.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
parity.ll
|
…
|
|
|
partial-fold32.ll
|
…
|
|
|
partial-fold64.ll
|
…
|
|
|
partition.ll
|
Add IR support, ELF section and user documentation for partitioning feature.
|
2019-05-29 03:29:01 +00:00 |
|
pass-three.ll
|
…
|
|
|
patchable-prologue.ll
|
…
|
|
|
patchpoint-invoke.ll
|
…
|
|
|
patchpoint-verifiable.mir
|
…
|
|
|
patchpoint-webkit_jscc.ll
|
…
|
|
|
patchpoint.ll
|
…
|
|
|
pause.ll
|
…
|
|
|
peep-setb.ll
|
…
|
|
|
peep-test-0.ll
|
…
|
|
|
peep-test-1.ll
|
…
|
|
|
peep-test-2.ll
|
…
|
|
|
peep-test-3.ll
|
…
|
|
|
peep-test-4.ll
|
…
|
|
|
peephole-cvt-sse.ll
|
…
|
|
|
peephole-fold-movsd.ll
|
[X86] Regenerate load fold peephole test.
|
2019-07-04 12:33:37 +00:00 |
|
peephole-fold-testrr.mir
|
[Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr)
|
2019-06-25 17:29:18 +00:00 |
|
peephole-multiple-folds.ll
|
…
|
|
|
peephole-na-phys-copy-folding.ll
|
…
|
|
|
peephole-recurrence.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
peephole.mir
|
Revert r359392 and r358887
|
2019-05-06 19:29:24 +00:00 |
|
personality.ll
|
…
|
|
|
personality_size.ll
|
…
|
|
|
phaddsub-extract.ll
|
[X86][SSE] lowerAddSubToHorizontalOp - enable ymm extraction+fold
|
2019-05-02 14:00:55 +00:00 |
|
phaddsub-undef.ll
|
[X86][SSE] LowerBuildVectorv4x32 - don't insert MOVQ for undef elts
|
2019-05-13 16:10:11 +00:00 |
|
phaddsub.ll
|
[X86] isHorizontalBinOp - add extract_subvector(shuffle(x)) handling (PR39921)
|
2019-06-02 15:47:49 +00:00 |
|
phi-bit-propagation.ll
|
…
|
|
|
phi-immediate-factoring.ll
|
…
|
|
|
phielim-split.ll
|
…
|
|
|
phys-reg-local-regalloc.ll
|
…
|
|
|
phys_subreg_coalesce-2.ll
|
…
|
|
|
phys_subreg_coalesce-3.ll
|
…
|
|
|
phys_subreg_coalesce.ll
|
…
|
|
|
physreg-pairs-error.ll
|
…
|
|
|
physreg-pairs.ll
|
…
|
|
|
pic-load-remat.ll
|
…
|
|
|
pic.ll
|
…
|
|
|
pic_jumptable.ll
|
…
|
|
|
pie.ll
|
…
|
|
|
pku.ll
|
[X86] Remove CustomInserters for RDPKRU/WRPKRU. Use some custom lowering and new ISD opcodes instead.
|
2019-04-04 00:28:49 +00:00 |
|
pmaddubsw.ll
|
…
|
|
|
pmovext.ll
|
…
|
|
|
pmovsx-inreg.ll
|
[x86] split 256-bit store of concatenated vectors
|
2019-06-04 16:40:04 +00:00 |
|
pmul.ll
|
[TargetLowering] SimplifyDemandedBits ZERO_EXTEND_VECTOR_INREG -> ANY_EXTEND_VECTOR_INREG
|
2019-06-25 12:57:43 +00:00 |
|
pmulh.ll
|
…
|
|
|
pmulld.ll
|
…
|
|
|
pointer-vector.ll
|
…
|
|
|
pop-stack-cleanup-msvc.ll
|
…
|
|
|
pop-stack-cleanup.ll
|
…
|
|
|
popcnt.ll
|
[X86] Add custom isel to select ADD/SUB/OR/XOR/AND to their non-immediate forms under optsize when the immediate has additional users.
|
2019-07-04 22:53:57 +00:00 |
|
post-ra-sched-with-debug.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
post-ra-sched.ll
|
…
|
|
|
postalloc-coalescing.ll
|
…
|
|
|
postra-ignore-dbg-instrs.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
postra-licm.ll
|
…
|
|
|
pow.75.ll
|
…
|
|
|
pow.ll
|
…
|
|
|
powi.ll
|
[X86] Regenerate powi tests to include i686 x87/sse targets
|
2019-03-22 18:04:28 +00:00 |
|
pr1462.ll
|
…
|
|
|
pr1489.ll
|
…
|
|
|
pr1505.ll
|
…
|
|
|
pr1505b.ll
|
…
|
|
|
pr2177.ll
|
…
|
|
|
pr2182.ll
|
…
|
|
|
pr2326.ll
|
…
|
|
|
pr2585.ll
|
…
|
|
|
pr2656.ll
|
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
|
2019-07-02 17:51:02 +00:00 |
|
pr2659.ll
|
…
|
|
|
pr2849.ll
|
…
|
|
|
pr2924.ll
|
…
|
|
|
pr2982.ll
|
…
|
|
|
pr3154.ll
|
…
|
|
|
pr3216.ll
|
…
|
|
|
pr3241.ll
|
…
|
|
|
pr3243.ll
|
…
|
|
|
pr3244.ll
|
…
|
|
|
pr3250.ll
|
…
|
|
|
pr3317.ll
|
…
|
|
|
pr3366.ll
|
…
|
|
|
pr3457.ll
|
…
|
|
|
pr3522.ll
|
…
|
|
|
pr5145.ll
|
[X86] Promote i8 CMOV's (PR40965)
|
2019-03-15 21:17:53 +00:00 |
|
pr7882.ll
|
…
|
|
|
pr9127.ll
|
…
|
|
|
pr9517.ll
|
…
|
|
|
pr9743.ll
|
…
|
|
|
pr10068.ll
|
…
|
|
|
pr10475.ll
|
…
|
|
|
pr10499.ll
|
…
|
|
|
pr10523.ll
|
…
|
|
|
pr10524.ll
|
…
|
|
|
pr10525.ll
|
…
|
|
|
pr10526.ll
|
…
|
|
|
pr11202.ll
|
…
|
|
|
pr11334.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
|
pr11415.ll
|
Reapply r359906, "RegAllocFast: Add heuristic to detect values not live-out of a block"
|
2019-05-03 19:06:57 +00:00 |
|
pr11468.ll
|
…
|
|
|
pr11985.ll
|
…
|
|
|
pr11998.ll
|
…
|
|
|
pr12360.ll
|
…
|
|
|
pr12889.ll
|
…
|
|
|
pr13209.ll
|
…
|
|
|
pr13220.ll
|
…
|
|
|
pr13458.ll
|
…
|
|
|
pr13577.ll
|
…
|
|
|
pr13859.ll
|
…
|
|
|
pr13899.ll
|
…
|
|
|
pr14088.ll
|
…
|
|
|
pr14098.ll
|
…
|
|
|
pr14161.ll
|
…
|
|
|
pr14204.ll
|
…
|
|
|
pr14314.ll
|
…
|
|
|
pr14333.ll
|
…
|
|
|
pr14562.ll
|
…
|
|
|
pr15267.ll
|
…
|
|
|
pr15296.ll
|
…
|
|
|
pr15309.ll
|
…
|
|
|
pr15705.ll
|
…
|
|
|
pr15981.ll
|
…
|
|
|
pr16031.ll
|
…
|
|
|
pr16360.ll
|
…
|
|
|
pr16807.ll
|
…
|
|
|
pr17546.ll
|
…
|
|
|
pr17631.ll
|
…
|
|
|
pr17764.ll
|
…
|
|
|
pr18014.ll
|
…
|
|
|
pr18054.ll
|
…
|
|
|
pr18162.ll
|
…
|
|
|
pr18344.ll
|
…
|
|
|
pr18846.ll
|
…
|
|
|
pr19049.ll
|
…
|
|
|
pr20011.ll
|
…
|
|
|
pr20012.ll
|
…
|
|
|
pr20020.ll
|
…
|
|
|
pr20088.ll
|
…
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pr21099.ll
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…
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pr21792.ll
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…
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pr22019.ll
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…
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pr22103.ll
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…
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pr22338.ll
|
[X86] Avoid icmp undef in reduced tests
|
2019-03-13 18:36:59 +00:00 |
|
pr22473.ll
|
[X86] Add test case for PR22473
|
2019-03-08 19:16:26 +00:00 |
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pr22774.ll
|
…
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pr22970.ll
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…
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pr23103.ll
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…
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pr23246.ll
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…
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pr23273.ll
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pr23603.ll
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pr23664.ll
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pr24139.ll
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…
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pr24374.ll
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pr24602.ll
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pr25828.ll
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pr26350.ll
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pr26625.ll
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pr26652.ll
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pr26757.ll
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pr26835.ll
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…
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pr26870.ll
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…
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pr27071.ll
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…
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pr27202.ll
|
[X86] Add custom isel to select ADD/SUB/OR/XOR/AND to their non-immediate forms under optsize when the immediate has additional users.
|
2019-07-04 22:53:57 +00:00 |
|
pr27501.ll
|
…
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pr27591.ll
|
RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs
|
2019-03-19 19:01:34 +00:00 |
|
pr27681.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
pr28129.ll
|
…
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pr28173.ll
|
…
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pr28444.ll
|
Revert rL357745: [SelectionDAG] Compute known bits of CopyFromReg
|
2019-04-10 18:00:41 +00:00 |
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pr28472.ll
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…
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pr28489.ll
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…
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pr28515.ll
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…
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pr28560.ll
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…
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pr28824.ll
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…
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pr29010.ll
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…
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pr29022.ll
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…
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pr29061.ll
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…
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pr29112.ll
|
[X86][AVX] combineX86ShufflesRecursively - peek through extract_subvector
|
2019-07-03 15:46:08 +00:00 |
|
pr29170.ll
|
…
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pr29222.ll
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…
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pr30284.ll
|
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
|
2019-06-25 10:51:15 +00:00 |
|
pr30290.ll
|
…
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pr30430.ll
|
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
|
2019-07-02 17:51:02 +00:00 |
|
pr30511.ll
|
…
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pr30562.ll
|
[SelectionDAG] Add SimplifyDemandedBits handling for ISD::SCALAR_TO_VECTOR
|
2019-03-15 17:00:55 +00:00 |
|
pr30813.ll
|
…
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pr30821.mir
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[X86] Introduce new MOVSSrm/MOVSDrm opcodes that use VR128 register class.
|
2019-06-18 03:23:11 +00:00 |
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pr31045.ll
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…
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pr31088.ll
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…
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pr31143.ll
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…
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pr31242.ll
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…
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pr31271.ll
|
[X86] Avoid icmp undef in reduced tests
|
2019-03-13 18:36:59 +00:00 |
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pr31323.ll
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…
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pr31593.ll
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…
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pr31773.ll
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pr31956.ll
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…
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pr32108.ll
|
…
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pr32241.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
pr32256.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
pr32278.ll
|
…
|
|
|
pr32282.ll
|
[SelectionDAG] Use KnownBits::computeForAddSub/computeForAddCarry
|
2019-04-15 07:19:11 +00:00 |
|
pr32284.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
pr32329.ll
|
[X86] Remove dead nodes left after ReplaceAllUsesWith calls during address matching
|
2019-04-24 18:02:07 +00:00 |
|
pr32340.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
pr32345.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
pr32368.ll
|
…
|
|
|
pr32420.ll
|
[X86] Promote i16 SRA instructions to i32
|
2019-04-05 06:32:50 +00:00 |
|
pr32451.ll
|
…
|
|
|
pr32484.ll
|
Reapply r359906, "RegAllocFast: Add heuristic to detect values not live-out of a block"
|
2019-05-03 19:06:57 +00:00 |
|
pr32515.ll
|
…
|
|
|
pr32588.ll
|
[X86] Avoid icmp undef in reduced tests
|
2019-03-13 18:36:59 +00:00 |
|
pr32610.ll
|
[x86] auto-generate complete test checks; NFC
|
2019-03-22 15:33:55 +00:00 |
|
pr32659.ll
|
…
|
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|
pr32907.ll
|
…
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|
|
pr33010.ll
|
Fix pr33010, a 2 year old crashing regression
|
2019-05-06 22:09:31 +00:00 |
|
pr33290.ll
|
…
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pr33349.ll
|
…
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pr33396.ll
|
…
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pr33715.ll
|
…
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pr33747.ll
|
…
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|
pr33828.ll
|
[X86] Avoid icmp undef in reduced tests
|
2019-03-13 18:36:59 +00:00 |
|
pr33954.ll
|
…
|
|
|
pr33960.ll
|
…
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|
pr34080-2.ll
|
[X86] Remove hasSideEffects=1 from the X87 pseudos with folded load.
|
2019-02-21 22:00:15 +00:00 |
|
pr34080.ll
|
[X86] Don't set exception mask bits when modifying FPCW to change rounding mode for fp->int conversion
|
2019-02-15 21:59:33 +00:00 |
|
pr34088.ll
|
…
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pr34137.ll
|
…
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pr34139.ll
|
…
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pr34149.ll
|
…
|
|
|
pr34177.ll
|
[X86][SSE] Constant fold PEXTRB/PEXTRW/EXTRACT_VECTOR_ELT nodes.
|
2019-03-16 15:02:00 +00:00 |
|
pr34271-1.ll
|
…
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pr34271.ll
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…
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pr34292.ll
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…
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pr34381.ll
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…
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pr34397.ll
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…
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pr34421.ll
|
…
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pr34592.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
pr34605.ll
|
…
|
|
|
pr34629.ll
|
…
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|
|
pr34634.ll
|
…
|
|
|
pr34653.ll
|
Reapply r359906, "RegAllocFast: Add heuristic to detect values not live-out of a block"
|
2019-05-03 19:06:57 +00:00 |
|
pr34657.ll
|
[X86][AVX] Add combineConcatVectors support to improve subvector handling
|
2019-03-13 16:37:30 +00:00 |
|
pr34855.ll
|
…
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pr35272.ll
|
…
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pr35316.ll
|
…
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pr35399.ll
|
…
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pr35443.ll
|
…
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pr35636.ll
|
…
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pr35761.ll
|
…
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pr35763.ll
|
…
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|
pr35765.ll
|
…
|
|
|
pr35918.ll
|
Recommit r354647 and r354648 "[LegalizeTypes] When promoting the result of EXTRACT_SUBVECTOR, also check if the input needs to be promoted. Use that to determine the element type to extract"
|
2019-02-23 19:51:32 +00:00 |
|
pr35972.ll
|
…
|
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|
pr35982.ll
|
…
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pr36199.ll
|
…
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pr36274.ll
|
…
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pr36312.ll
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…
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pr36553.ll
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…
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pr36602.ll
|
…
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pr36865.ll
|
…
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pr37063.ll
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…
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pr37264.ll
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…
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pr37359.ll
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…
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pr37499.ll
|
…
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pr37820.ll
|
…
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pr37826.ll
|
…
|
|
|
pr37879.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
pr37916.ll
|
…
|
|
|
pr38038.ll
|
…
|
|
|
pr38185.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
pr38217.ll
|
…
|
|
|
pr38533.ll
|
…
|
|
|
pr38539.ll
|
[X86] Avoid icmp undef in reduced tests
|
2019-03-13 18:36:59 +00:00 |
|
pr38639.ll
|
…
|
|
|
pr38738.ll
|
…
|
|
|
pr38743.ll
|
This reverts r365061 and r365062 (test update)
|
2019-07-05 12:42:06 +00:00 |
|
pr38762.ll
|
…
|
|
|
pr38763.ll
|
…
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pr38795.ll
|
…
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pr38803.ll
|
…
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pr38819.ll
|
…
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pr38865-2.ll
|
…
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|
|
pr38865-3.ll
|
…
|
|
|
pr38865.ll
|
…
|
|
|
pr38952.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
pr39098.ll
|
…
|
|
|
pr39187-g.ll
|
…
|
|
|
pr39243.ll
|
[DebugInfo] Combine Trivial and NonTrivial flags
|
2019-04-11 20:25:10 +00:00 |
|
pr39666.ll
|
[ScalarizeMaskedMemIntrin] Add support for scalarizing expandload and compressstore intrinsics.
|
2019-03-21 17:38:52 +00:00 |
|
pr39733.ll
|
…
|
|
|
pr39896.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
pr39926.ll
|
…
|
|
|
pr40090.ll
|
…
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|
pr40289-64bit.ll
|
…
|
|
|
pr40289.ll
|
…
|
|
|
pr40529.ll
|
[X86] Don't set exception mask bits when modifying FPCW to change rounding mode for fp->int conversion
|
2019-02-15 21:59:33 +00:00 |
|
pr40539.ll
|
…
|
|
|
pr40631_deadstore_elision.ll
|
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
|
2019-03-13 17:07:09 +00:00 |
|
pr40730.ll
|
[X86][AVX] lowerShuffleAsLanePermuteAndPermute - fully populate the lane shuffle mask (PR40730)
|
2019-02-15 11:39:21 +00:00 |
|
pr40737.ll
|
[X86] Fix LowerAsmOutputForConstraint.
|
2019-02-15 20:01:55 +00:00 |
|
pr40811.ll
|
Recommit r354363 "[X86][SSE] Generalize X86ISD::BLENDI support to more value types"
|
2019-02-23 21:41:42 +00:00 |
|
pr40891.ll
|
[X86] Add test case that was supposed to go with r355116.
|
2019-02-28 18:50:16 +00:00 |
|
pr40994.ll
|
[ScalarizeMaskedMemIntrin] Add support for scalarizing expandload and compressstore intrinsics.
|
2019-03-21 17:38:52 +00:00 |
|
pr41619.ll
|
[X86] Add test case for mask register variant of PR41619 which should be fixed after r360552
|
2019-05-13 15:45:20 +00:00 |
|
pr41678.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
pr41748.ll
|
[SelectionDAG][X86] Support inline assembly returning an mmx register into a type with fewer than 64 bits.
|
2019-05-06 19:50:14 +00:00 |
|
pr42452.ll
|
[X86] Improve the type checking fast-isel handling of vector bitcasts.
|
2019-07-01 07:09:34 +00:00 |
|
pr42565.ll
|
[X86] Don't convert 8 or 16 bit ADDs to LEAs on Atom in FixupLEAPass.
|
2019-07-11 01:01:39 +00:00 |
|
pr42616.ll
|
[X86] Remove offset of 8 from the call to FuseInst for UNPCKLPDrr folding added in r365287.
|
2019-07-14 04:13:33 +00:00 |
|
pre-coalesce-2.ll
|
…
|
|
|
pre-coalesce.ll
|
…
|
|
|
pre-coalesce.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
pre-ra-sched.ll
|
…
|
|
|
prefer-avx256-lzcnt.ll
|
…
|
|
|
prefer-avx256-mask-extend.ll
|
[X86] Move VPTESTM matching from the isel table to custom code in X86ISelDAGToDAG.
|
2019-04-14 18:26:11 +00:00 |
|
prefer-avx256-mask-shuffle.ll
|
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
|
2019-06-25 10:51:15 +00:00 |
|
prefer-avx256-popcnt.ll
|
…
|
|
|
prefer-avx256-shift.ll
|
…
|
|
|
prefer-avx256-trunc.ll
|
…
|
|
|
prefer-avx256-wide-mul.ll
|
…
|
|
|
prefetch.ll
|
…
|
|
|
prefixdata.ll
|
…
|
|
|
preserve_allcc64.ll
|
…
|
|
|
preserve_mostcc64.ll
|
…
|
|
|
private-2.ll
|
…
|
|
|
private.ll
|
…
|
|
|
probe-stack-x32.ll
|
[X86] Fix stack probing on x32 (PR41477)
|
2019-04-20 07:25:46 +00:00 |
|
prolog-push-seq.ll
|
…
|
|
|
prologepilog_deref_size.mir
|
Describe stack-id as an enum
|
2019-06-17 09:13:29 +00:00 |
|
prologue-epilogue-remarks.mir
|
…
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|
|
prologuedata.ll
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…
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|
|
promote-assert-zext.ll
|
…
|
|
|
promote-i16.ll
|
…
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|
|
promote-trunc.ll
|
…
|
|
|
promote-vec3.ll
|
[X86] Rework the logic in LowerBuildVectorv16i8 to make better use of any_extend and break false dependencies. Other improvements
|
2019-06-26 20:16:19 +00:00 |
|
promote.ll
|
[X86] Regenerate promote.ll. NFC.
|
2019-06-18 10:10:53 +00:00 |
|
ps4-noreturn.ll
|
…
|
|
|
ps4-ssp-nop.ll
|
[PS4] Emit a trap after a stack-protector fail call.
|
2019-03-06 19:57:43 +00:00 |
|
pseudo_cmov_lower.ll
|
…
|
|
|
pseudo_cmov_lower1.ll
|
…
|
|
|
pseudo_cmov_lower2.ll
|
[X86] Avoid codegen changes when DBG_VALUE appears between lowered selects
|
2019-03-04 10:56:02 +00:00 |
|
pshufb-mask-comments.ll
|
…
|
|
|
pshufd-combine-crash.ll
|
…
|
|
|
psubus.ll
|
[SDAG] commute setcc operands to match a subtract
|
2019-07-10 23:23:54 +00:00 |
|
ptest.ll
|
…
|
|
|
ptr-rotate.ll
|
…
|
|
|
ptrtoint-constexpr.ll
|
…
|
|
|
ptrtoint-narrow.ll
|
[AsmPrinter] Treat a narrowing PtrToInt like Trunc
|
2019-05-23 16:29:09 +00:00 |
|
ptwrite32-intrinsic.ll
|
…
|
|
|
ptwrite64-intrinsic.ll
|
…
|
|
|
pull-binop-through-shift.ll
|
[DAGCombiner] visitShiftByConstant(): drop bogus signbit check
|
2019-05-17 15:52:58 +00:00 |
|
pull-conditional-binop-through-shift.ll
|
[NFC] Fixup FileCheck option name in tests added in rL360881
|
2019-05-16 12:39:34 +00:00 |
|
push-cfi-debug.ll
|
…
|
|
|
push-cfi-obj.ll
|
[llvm-readobj] Change -long-option to --long-option in tests. NFC
|
2019-05-01 05:27:20 +00:00 |
|
push-cfi.ll
|
…
|
|
|
ragreedy-bug.ll
|
Codegen: Fixed perf branch_weights in couple of tests. NFC.
|
2019-04-15 09:30:31 +00:00 |
|
ragreedy-hoist-spill.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
ragreedy-last-chance-recoloring.ll
|
…
|
|
|
rd-mod-wr-eflags.ll
|
[CGP] add special-cases to form unsigned add with overflow (PR40486)
|
2019-02-24 15:31:27 +00:00 |
|
rdpid.ll
|
…
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|
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rdpmc.ll
|
…
|
|
|
rdrand-x86_64.ll
|
…
|
|
|
rdrand.ll
|
[X86] Remove FeatureSlowIncDec from Sandy Bridge and later Intel Core CPUs
|
2019-02-20 05:39:11 +00:00 |
|
rdseed-x86_64.ll
|
…
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|
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rdseed.ll
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…
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rdtsc-upgrade.ll
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…
|
|
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rdtsc.ll
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…
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|
|
read-fp-no-frame-pointer.ll
|
…
|
|
|
recip-fastmath.ll
|
…
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|
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recip-fastmath2.ll
|
…
|
|
|
recip-pic.ll
|
…
|
|
|
red-zone.ll
|
…
|
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|
red-zone2.ll
|
…
|
|
|
reduce-trunc-shl.ll
|
[x86] split more v8f32/v8i32 shuffles in lowering
|
2019-02-18 16:46:12 +00:00 |
|
regalloc-advanced-split-cost.ll
|
…
|
|
|
regalloc-copy-hints.mir
|
Describe stack-id as an enum
|
2019-06-17 09:13:29 +00:00 |
|
regalloc-fast-missing-live-out-spill.mir
|
RegAllocFast: Set MayLiveAcrossBlocks when allocating uses
|
2019-05-27 20:37:31 +00:00 |
|
regalloc-reconcile-broken-hints.ll
|
…
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regalloc-spill-at-ehpad.ll
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…
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|
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regcall-no-plt.ll
|
…
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reghinting.ll
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…
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regparm.ll
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…
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regpressure.ll
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…
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rem.ll
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…
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rem_crash.ll
|
…
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|
remarks-section.ll
|
[Remarks] Add string deduplication using a string table
|
2019-04-24 00:06:24 +00:00 |
|
remat-constant.ll
|
…
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|
|
remat-fold-load.ll
|
…
|
|
|
remat-mov-0.ll
|
…
|
|
|
remat-phys-dead.ll
|
…
|
|
|
remat-scalar-zero.ll
|
…
|
|
|
replace-load-and-with-bzhi.ll
|
…
|
|
|
replace_unsupported_masked_mem_intrin.ll
|
…
|
|
|
ret-addr.ll
|
…
|
|
|
ret-i64-0.ll
|
…
|
|
|
ret-mmx.ll
|
…
|
|
|
retpoline-external.ll
|
…
|
|
|
retpoline-regparm.ll
|
…
|
|
|
retpoline.ll
|
…
|
|
|
return-ext.ll
|
…
|
|
|
return_zeroext_i2.ll
|
…
|
|
|
returned-trunc-tail-calls.ll
|
…
|
|
|
reverse_branches.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
rip-rel-address.ll
|
…
|
|
|
rip-rel-lea.ll
|
…
|
|
|
rodata-relocs.ll
|
…
|
|
|
rot16.ll
|
…
|
|
|
rot32.ll
|
[X86] Add post-isel pseudos for rotate by immediate using SHLD/SHRD
|
2019-03-27 17:29:34 +00:00 |
|
rot64.ll
|
[X86] Add post-isel pseudos for rotate by immediate using SHLD/SHRD
|
2019-03-27 17:29:34 +00:00 |
|
rotate-extract-vector.ll
|
[X86] lowerBuildVectorToBitOp - support build_vector(shift()) -> shift(build_vector(),C)
|
2019-05-25 18:02:17 +00:00 |
|
rotate-extract.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
rotate-multi.ll
|
Add more rotate tests, including ORs of rotates
|
2019-03-21 17:14:22 +00:00 |
|
rotate.ll
|
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
|
2019-03-13 17:07:09 +00:00 |
|
rotate2.ll
|
…
|
|
|
rotate4.ll
|
[x86] make 8-bit shl undesirable
|
2019-04-08 13:58:50 +00:00 |
|
rotate_vec.ll
|
…
|
|
|
rounding-ops.ll
|
…
|
|
|
rrlist-livereg-corrutpion.ll
|
…
|
|
|
rtm.ll
|
…
|
|
|
sad.ll
|
[DAGCombiner] narrow vector binop with inserts/extract
|
2019-05-13 14:31:14 +00:00 |
|
sad_variations.ll
|
…
|
|
|
sadd_sat.ll
|
[X86] Promote i8 CMOV's (PR40965)
|
2019-03-15 21:17:53 +00:00 |
|
sadd_sat_vec.ll
|
[X86][AVX] isNOT - handle concat_vectors(xor X, -1, xor Y, -1) pattern
|
2019-06-21 10:44:15 +00:00 |
|
saddo-redundant-add.ll
|
…
|
|
|
safestack.ll
|
…
|
|
|
safestack_inline.ll
|
…
|
|
|
safestack_ssp.ll
|
…
|
|
|
sandybridge-loads.ll
|
[x86] avoid vector load narrowing with extracted store uses (PR42305)
|
2019-06-19 18:13:47 +00:00 |
|
sar_fold.ll
|
…
|
|
|
sar_fold64.ll
|
…
|
|
|
sat-add.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
sbb.ll
|
…
|
|
|
scalar-extract.ll
|
…
|
|
|
scalar-fp-to-i64.ll
|
[X86] Convert f32/f64 FANDN/FAND/FOR/FXOR to vector logic ops and scalar_to_vector/extract_vector_elts to reduce isel patterns.
|
2019-06-10 00:41:07 +00:00 |
|
scalar-int-to-fp.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
scalar-min-max-fill-operand.ll
|
…
|
|
|
scalar_sse_minmax.ll
|
…
|
|
|
scalar_widen_div.ll
|
…
|
|
|
scalarize-bitcast.ll
|
…
|
|
|
scalarize-fp.ll
|
[DAGCombiner] generalize binop-of-splats scalarization
|
2019-04-23 13:16:41 +00:00 |
|
scatter-schedule.ll
|
…
|
|
|
scavenger.mir
|
…
|
|
|
scev-interchange.ll
|
…
|
|
|
scheduler-backtracking.ll
|
[DAGCombiner] Combine OR as ADD when no common bits are set
|
2019-04-23 10:01:08 +00:00 |
|
sdiv-exact.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
sdiv-pow2.ll
|
…
|
|
|
section_mergeable_size.ll
|
…
|
|
|
segmented-stacks-dynamic.ll
|
…
|
|
|
segmented-stacks-standalone.ll
|
…
|
|
|
segmented-stacks.ll
|
…
|
|
|
seh-catch-all-win32.ll
|
…
|
|
|
seh-catch-all.ll
|
…
|
|
|
seh-catchpad.ll
|
…
|
|
|
seh-except-finally.ll
|
…
|
|
|
seh-exception-code.ll
|
…
|
|
|
seh-filter-no-personality.ll
|
…
|
|
|
seh-finally.ll
|
…
|
|
|
seh-localaddress.ll
|
…
|
|
|
seh-no-invokes.ll
|
…
|
|
|
seh-safe-div-win32.ll
|
…
|
|
|
seh-safe-div.ll
|
…
|
|
|
seh-stack-realign.ll
|
…
|
|
|
select-1-or-neg1.ll
|
…
|
|
|
select-mmx.ll
|
…
|
|
|
select-of-fp-constants.ll
|
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
|
2019-07-02 17:51:02 +00:00 |
|
select-with-and-or.ll
|
…
|
|
|
select.ll
|
Teach the DAGCombine to fold this pattern(c1 and c2 is constant).
|
2019-06-26 05:12:53 +00:00 |
|
select_const.ll
|
[x86] make 8-bit shl undesirable
|
2019-04-08 13:58:50 +00:00 |
|
select_meta.ll
|
…
|
|
|
selectcc-to-shiftand.ll
|
…
|
|
|
selectiondag-crash.ll
|
…
|
|
|
selectiondag-cse.ll
|
…
|
|
|
selectiondag-debug-loc.ll
|
…
|
|
|
selectiondag-dominator.ll
|
…
|
|
|
selectiondag-order.ll
|
…
|
|
|
setcc-combine.ll
|
…
|
|
|
setcc-logic.ll
|
…
|
|
|
setcc-lowering.ll
|
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
|
2019-06-25 10:51:15 +00:00 |
|
setcc-narrowing.ll
|
…
|
|
|
setcc-wide-types.ll
|
[X86] Don't compare i128 through vector if construction not cheap (PR41971)
|
2019-05-22 06:47:06 +00:00 |
|
setcc.ll
|
…
|
|
|
setjmp-spills.ll
|
…
|
|
|
setoeq.ll
|
…
|
|
|
setuge.ll
|
…
|
|
|
sext-i1.ll
|
[DAGCombiner] fold sext into decrement
|
2019-03-29 13:49:08 +00:00 |
|
sext-load.ll
|
…
|
|
|
sext-ret-val.ll
|
…
|
|
|
sext-setcc-self.ll
|
…
|
|
|
sext-subreg.ll
|
…
|
|
|
sext-trunc.ll
|
…
|
|
|
sha.ll
|
…
|
|
|
shadow-stack.ll
|
…
|
|
|
shift-amount-mod.ll
|
[DAGCombine][X86][AArch64][MIPS][LANAI] (C - x) - y -> C - (x + y) fold (PR41952)
|
2019-06-04 11:06:21 +00:00 |
|
shift-and-x86_64.ll
|
…
|
|
|
shift-and.ll
|
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
|
2019-03-13 17:07:09 +00:00 |
|
shift-avx2-crash.ll
|
…
|
|
|
shift-bmi2.ll
|
…
|
|
|
shift-coalesce.ll
|
…
|
|
|
shift-codegen.ll
|
…
|
|
|
shift-combine-crash.ll
|
…
|
|
|
shift-combine.ll
|
…
|
|
|
shift-double-x86_64.ll
|
[X86] Improve use of SHLD/SHRD
|
2019-03-02 02:44:16 +00:00 |
|
shift-double.ll
|
[X86] Improve use of SHLD/SHRD
|
2019-03-02 02:44:16 +00:00 |
|
shift-folding.ll
|
…
|
|
|
shift-i128.ll
|
…
|
|
|
shift-i256.ll
|
…
|
|
|
shift-mask.ll
|
[X86] Disable shouldFoldConstantShiftPairToMask for scalar shifts on AMD targets (PR40758)
|
2019-05-14 15:21:28 +00:00 |
|
shift-one.ll
|
…
|
|
|
shift-pair.ll
|
…
|
|
|
shift-parts.ll
|
…
|
|
|
shift-pcmp.ll
|
…
|
|
|
shift_minsize.ll
|
…
|
|
|
shl-anyext.ll
|
…
|
|
|
shl-crash-on-legalize.ll
|
…
|
|
|
shl-i64.ll
|
…
|
|
|
shl_elim.ll
|
…
|
|
|
shl_undef.ll
|
…
|
|
|
shrink-compare.ll
|
…
|
|
|
shrink-fp-const1.ll
|
…
|
|
|
shrink-fp-const2.ll
|
…
|
|
|
shrink-wrap-chkstk-x86_64.ll
|
[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
|
2019-06-13 13:56:19 +00:00 |
|
shrink-wrap-chkstk.ll
|
…
|
|
|
shrink-wrapping-vla.ll
|
…
|
|
|
shrink_vmul-widen.ll
|
[x86] split 256-bit store of concatenated vectors
|
2019-06-04 16:40:04 +00:00 |
|
shrink_vmul.ll
|
[x86] split 256-bit store of concatenated vectors
|
2019-06-04 16:40:04 +00:00 |
|
shrink_vmul_sse.ll
|
…
|
|
|
shrink_wrap_dbg_value.mir
|
Describe stack-id as an enum
|
2019-06-17 09:13:29 +00:00 |
|
shrinkwrap-hang.ll
|
…
|
|
|
shuffle-combine-crash-2.ll
|
…
|
|
|
shuffle-combine-crash.ll
|
…
|
|
|
shuffle-extract-subvector.ll
|
[DAGCombine] Fix a miscompile when reducing BUILD_VECTORs to a shuffle
|
2019-03-19 16:52:00 +00:00 |
|
shuffle-of-insert.ll
|
…
|
|
|
shuffle-of-splat-multiuses.ll
|
…
|
|
|
shuffle-strided-with-offset-128.ll
|
…
|
|
|
shuffle-strided-with-offset-256.ll
|
[X86][AVX] Combine non-lane crossing binary shuffles using X86ISD::VPERMV3
|
2019-04-28 14:31:01 +00:00 |
|
shuffle-strided-with-offset-512.ll
|
[X86][AVX] X86ISD::PERMV/PERMV3 node types can never fold index ops
|
2019-04-16 19:18:53 +00:00 |
|
shuffle-vs-trunc-128-widen.ll
|
…
|
|
|
shuffle-vs-trunc-128.ll
|
…
|
|
|
shuffle-vs-trunc-256-widen.ll
|
[X86][AVX] Combine non-lane crossing binary shuffles using X86ISD::VPERMV3
|
2019-04-28 14:31:01 +00:00 |
|
shuffle-vs-trunc-256.ll
|
[X86][AVX] Combine non-lane crossing binary shuffles using X86ISD::VPERMV3
|
2019-04-28 14:31:01 +00:00 |
|
shuffle-vs-trunc-512-widen.ll
|
[X86][AVX] combineX86ShufflesRecursively - peek through extract_subvector
|
2019-07-03 15:46:08 +00:00 |
|
shuffle-vs-trunc-512.ll
|
[X86][AVX] combineX86ShufflesRecursively - peek through extract_subvector
|
2019-07-03 15:46:08 +00:00 |
|
sibcall-2.ll
|
…
|
|
|
sibcall-3.ll
|
…
|
|
|
sibcall-4.ll
|
…
|
|
|
sibcall-5.ll
|
…
|
|
|
sibcall-6.ll
|
…
|
|
|
sibcall-byval.ll
|
…
|
|
|
sibcall-win64.ll
|
…
|
|
|
sibcall.ll
|
[Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr)
|
2019-06-25 17:29:18 +00:00 |
|
signbit-shift.ll
|
[DAGCombiner] Combine OR as ADD when no common bits are set
|
2019-04-23 10:01:08 +00:00 |
|
signed-truncation-check.ll
|
[X86] Suppress load folding for add/sub with 128 immediate.
|
2019-03-06 07:36:36 +00:00 |
|
simple-register-allocation-read-undef.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
simple-zext.ll
|
…
|
|
|
sincos-opt.ll
|
…
|
|
|
sincos.ll
|
…
|
|
|
sink-addsub-of-const.ll
|
[DAGCombine][X86][AArch64][MIPS][LANAI] (C - x) - y -> C - (x + y) fold (PR41952)
|
2019-06-04 11:06:21 +00:00 |
|
sink-blockfreq.ll
|
…
|
|
|
sink-cheap-instructions.ll
|
…
|
|
|
sink-gep-before-mem-inst.ll
|
…
|
|
|
sink-hoist.ll
|
…
|
|
|
sink-local-value.ll
|
…
|
|
|
sink-out-of-loop.ll
|
…
|
|
|
sitofp.ll
|
…
|
|
|
sjlj-baseptr.ll
|
…
|
|
|
sjlj-eh.ll
|
…
|
|
|
sjlj-shadow-stack-liveness.mir
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
sjlj.ll
|
…
|
|
|
slow-incdec.ll
|
…
|
|
|
slow-pmulld.ll
|
Revert rL356864 : [X86][SSE41] Start shuffle combining from ZERO_EXTEND_VECTOR_INREG (PR40685)
|
2019-03-27 10:25:02 +00:00 |
|
slow-unaligned-mem.ll
|
[X86] AMD znver2 enablement
|
2019-02-26 16:55:10 +00:00 |
|
small-byval-memcpy.ll
|
…
|
|
|
smul-with-overflow.ll
|
…
|
|
|
smul_fix.ll
|
…
|
|
|
smul_fix_sat.ll
|
[LegalizeTypes] Fix saturation bug for smul.fix.sat
|
2019-07-09 10:24:50 +00:00 |
|
smul_fix_sat_constants.ll
|
[Intrinsic] Signed Fixed Point Saturation Multiplication Intrinsic
|
2019-05-21 19:17:19 +00:00 |
|
soft-fp-legal-in-HW-reg.ll
|
…
|
|
|
soft-fp.ll
|
…
|
|
|
soft-sitofp.ll
|
…
|
|
|
speculative-load-hardening-call-and-ret.ll
|
…
|
|
|
speculative-load-hardening-gather.ll
|
…
|
|
|
speculative-load-hardening-indirect.ll
|
X86: regenerate speculative-load-hardening-indirect.ll tests. NFC.
|
2019-04-02 22:44:46 +00:00 |
|
speculative-load-hardening.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
splat-const.ll
|
…
|
|
|
splat-for-size.ll
|
…
|
|
|
split-eh-lpad-edges.ll
|
…
|
|
|
split-extend-vector-inreg.ll
|
…
|
|
|
split-store.ll
|
[DAGCombiner] Combine OR as ADD when no common bits are set
|
2019-04-23 10:01:08 +00:00 |
|
split-vector-bitcast.ll
|
…
|
|
|
split-vector-rem.ll
|
…
|
|
|
sqrt-fastmath-mir.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
sqrt-fastmath-tune.ll
|
…
|
|
|
sqrt-fastmath.ll
|
…
|
|
|
sqrt-partial.ll
|
…
|
|
|
sqrt.ll
|
…
|
|
|
sret-implicit.ll
|
…
|
|
|
sse-align-0.ll
|
…
|
|
|
sse-align-1.ll
|
…
|
|
|
sse-align-2.ll
|
…
|
|
|
sse-align-3.ll
|
…
|
|
|
sse-align-4.ll
|
…
|
|
|
sse-align-5.ll
|
…
|
|
|
sse-align-6.ll
|
…
|
|
|
sse-align-7.ll
|
…
|
|
|
sse-align-8.ll
|
…
|
|
|
sse-align-9.ll
|
…
|
|
|
sse-align-10.ll
|
…
|
|
|
sse-align-11.ll
|
…
|
|
|
sse-align-12.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
sse-commute.ll
|
…
|
|
|
sse-cvttp2si.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
sse-domains.ll
|
…
|
|
|
sse-fcopysign.ll
|
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
|
2019-07-02 17:51:02 +00:00 |
|
sse-fsignum.ll
|
…
|
|
|
sse-intel-ocl.ll
|
…
|
|
|
sse-intrinsics-fast-isel-x86_64.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
sse-intrinsics-fast-isel.ll
|
[X86] Separate the memory size of vzext_load/vextract_store from the element size of the result type. Use them improve the codegen of v2f32 loads/stores with sse1 only.
|
2019-07-15 02:02:31 +00:00 |
|
sse-intrinsics-x86-upgrade.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
sse-intrinsics-x86.ll
|
…
|
|
|
sse-intrinsics-x86_64-upgrade.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
sse-intrinsics-x86_64.ll
|
…
|
|
|
sse-load-ret.ll
|
…
|
|
|
sse-minmax.ll
|
[DAGCombine] SimplifySelectCC - call FoldSetCC with the setcc result type
|
2019-03-21 14:07:18 +00:00 |
|
sse-only.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
|
sse-regcall.ll
|
…
|
|
|
sse-scalar-fp-arith-unary.ll
|
…
|
|
|
sse-scalar-fp-arith.ll
|
[X86] Add load folding isel patterns to scalar_math_patterns and AVX512_scalar_math_fp_patterns.
|
2019-06-11 04:30:53 +00:00 |
|
sse-unaligned-mem-feature.ll
|
…
|
|
|
sse-varargs.ll
|
…
|
|
|
sse1-fcopysign.ll
|
…
|
|
|
sse1.ll
|
…
|
|
|
sse2-intrinsics-canonical.ll
|
…
|
|
|
sse2-intrinsics-fast-isel-x86_64.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
sse2-intrinsics-fast-isel.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
sse2-intrinsics-x86-upgrade.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
sse2-intrinsics-x86.ll
|
[X86] Restore the pavg intrinsics.
|
2019-04-15 17:17:35 +00:00 |
|
sse2-intrinsics-x86_64-upgrade.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
sse2-intrinsics-x86_64.ll
|
…
|
|
|
sse2-vector-shifts.ll
|
[X86][SSE] Disable shouldFoldConstantShiftPairToMask for btver1/btver2 targets (PR40758)
|
2019-04-26 10:49:13 +00:00 |
|
sse2.ll
|
[X86] Make movsd commutable to shufpd with a 0x02 immediate on pre-SSE4.1 targets.
|
2019-07-08 06:52:43 +00:00 |
|
sse3-avx-addsub-2.ll
|
…
|
|
|
sse3-avx-addsub.ll
|
…
|
|
|
sse3-intrinsics-fast-isel.ll
|
…
|
|
|
sse3-intrinsics-x86.ll
|
[X86] Remove CustomInserter pseudos for MONITOR/MONITORX/CLZERO. Use custom instruction selection instead.
|
2019-04-03 23:28:30 +00:00 |
|
sse3.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
|
sse4a-intrinsics-fast-isel.ll
|
…
|
|
|
sse4a-upgrade.ll
|
…
|
|
|
sse4a.ll
|
…
|
|
|
sse41-intrinsics-fast-isel.ll
|
…
|
|
|
sse41-intrinsics-x86-upgrade.ll
|
…
|
|
|
sse41-intrinsics-x86.ll
|
…
|
|
|
sse41-pmovxrm.ll
|
…
|
|
|
sse41.ll
|
…
|
|
|
sse42-intrinsics-fast-isel-x86_64.ll
|
…
|
|
|
sse42-intrinsics-fast-isel.ll
|
…
|
|
|
sse42-intrinsics-x86.ll
|
…
|
|
|
sse42-intrinsics-x86_64.ll
|
…
|
|
|
sse_partial_update.ll
|
…
|
|
|
sse_reload_fold.ll
|
…
|
|
|
ssp-data-layout.ll
|
…
|
|
|
ssp-guard-spill.ll
|
…
|
|
|
ssse3-intrinsics-fast-isel.ll
|
…
|
|
|
ssse3-intrinsics-x86.ll
|
…
|
|
|
ssub_sat.ll
|
[X86] Promote i8 CMOV's (PR40965)
|
2019-03-15 21:17:53 +00:00 |
|
ssub_sat_vec.ll
|
[X86][AVX] isNOT - handle concat_vectors(xor X, -1, xor Y, -1) pattern
|
2019-06-21 10:44:15 +00:00 |
|
stack-align-memcpy.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
stack-align.ll
|
…
|
|
|
stack-align2.ll
|
…
|
|
|
stack-folding-3dnow.ll
|
…
|
|
|
stack-folding-adx-x86_64.ll
|
…
|
|
|
stack-folding-adx.mir
|
[X86] Merge the different SETcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:27:49 +00:00 |
|
stack-folding-avx512bf16.ll
|
[X86] Add AVX512BF16 and AVX512VP2INTERSECT instructions to the loading folding tables.
|
2019-06-01 06:20:59 +00:00 |
|
stack-folding-avx512vp2intersect.ll
|
[X86] Add AVX512BF16 and AVX512VP2INTERSECT instructions to the loading folding tables.
|
2019-06-01 06:20:59 +00:00 |
|
stack-folding-bmi.ll
|
…
|
|
|
stack-folding-bmi2.ll
|
…
|
|
|
stack-folding-bmi2.mir
|
…
|
|
|
stack-folding-fp-avx1.ll
|
[X86] Don't prevent load folding for cvtsi2ss/cvtsi2sd based on hasPartialRegUpdate.
|
2019-02-16 03:34:54 +00:00 |
|
stack-folding-fp-avx512.ll
|
[X86] Make a bunch of merge masked binops commutable for loading folding.
|
2019-06-06 21:00:04 +00:00 |
|
stack-folding-fp-avx512vl.ll
|
…
|
|
|
stack-folding-fp-sse42.ll
|
[X86] Don't prevent load folding for cvtsi2ss/cvtsi2sd based on hasPartialRegUpdate.
|
2019-02-16 03:34:54 +00:00 |
|
stack-folding-int-avx1.ll
|
…
|
|
|
stack-folding-int-avx2.ll
|
[x86] make stack folding tests immune to unrelated transforms; NFC
|
2019-04-03 16:33:24 +00:00 |
|
stack-folding-int-avx512.ll
|
[X86] Make a bunch of merge masked binops commutable for loading folding.
|
2019-06-06 21:00:04 +00:00 |
|
stack-folding-int-avx512vl.ll
|
…
|
|
|
stack-folding-int-sse42.ll
|
…
|
|
|
stack-folding-lwp.ll
|
…
|
|
|
stack-folding-mmx.ll
|
…
|
|
|
stack-folding-sha.ll
|
…
|
|
|
stack-folding-tbm.ll
|
…
|
|
|
stack-folding-x86_64.ll
|
…
|
|
|
stack-folding-xop.ll
|
…
|
|
|
stack-probe-red-zone.ll
|
…
|
|
|
stack-probe-size.ll
|
…
|
|
|
stack-probes.ll
|
…
|
|
|
stack-protector-dbginfo.ll
|
…
|
|
|
stack-protector-msvc.ll
|
…
|
|
|
stack-protector-remarks.ll
|
…
|
|
|
stack-protector-target.ll
|
…
|
|
|
stack-protector-vreg-to-vreg-copy.ll
|
…
|
|
|
stack-protector-weight.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
stack-protector.ll
|
StackProtector: Use PointerMayBeCaptured
|
2019-06-12 14:23:33 +00:00 |
|
stack-size-section-function-sections.ll
|
…
|
|
|
stack-size-section.ll
|
…
|
|
|
stack-update-frame-opcode.ll
|
…
|
|
|
stack_guard_remat.ll
|
…
|
|
|
stackguard-internal.ll
|
…
|
|
|
stackmap-fast-isel.ll
|
…
|
|
|
stackmap-frame-setup.ll
|
…
|
|
|
stackmap-large-constants.ll
|
…
|
|
|
stackmap-large-location-size.ll
|
…
|
|
|
stackmap-liveness.ll
|
…
|
|
|
stackmap-nops.ll
|
…
|
|
|
stackmap-shadow-optimization.ll
|
…
|
|
|
stackmap.ll
|
…
|
|
|
stackpointer.ll
|
…
|
|
|
statepoint-allocas.ll
|
…
|
|
|
statepoint-call-lowering.ll
|
…
|
|
|
statepoint-far-call.ll
|
…
|
|
|
statepoint-forward.ll
|
…
|
|
|
statepoint-gctransition-call-lowering.ll
|
…
|
|
|
statepoint-invoke.ll
|
…
|
|
|
statepoint-live-in.ll
|
[Tests] A few more live-in deopt lowering tests
|
2019-02-12 23:00:07 +00:00 |
|
statepoint-stack-usage.ll
|
…
|
|
|
statepoint-stackmap-format.ll
|
…
|
|
|
statepoint-uniqueing.ll
|
…
|
|
|
statepoint-vector-bad-spill.ll
|
…
|
|
|
statepoint-vector.ll
|
…
|
|
|
stdarg.ll
|
…
|
|
|
stdcall-notailcall.ll
|
…
|
|
|
stdcall.ll
|
…
|
|
|
store-empty-member.ll
|
…
|
|
|
store-fp-constant.ll
|
…
|
|
|
store-global-address.ll
|
…
|
|
|
store-narrow.ll
|
…
|
|
|
store-zero-and-minus-one.ll
|
…
|
|
|
store_op_load_fold.ll
|
…
|
|
|
store_op_load_fold2.ll
|
…
|
|
|
stores-merging.ll
|
[DAGCombine] Fold overlapping constant stores
|
2019-02-22 16:00:19 +00:00 |
|
storetrunc-fp.ll
|
…
|
|
|
stride-nine-with-base-reg.ll
|
…
|
|
|
stride-reuse.ll
|
…
|
|
|
sttni.ll
|
…
|
|
|
sub-of-not.ll
|
[Codegen][X86][AArch64][ARM][PowerPC] Inc-of-add vs sub-of-not (PR42457)
|
2019-07-03 09:41:35 +00:00 |
|
sub-with-overflow.ll
|
[DAGCombiner][X86][SystemZ] Canonicalize SSUBO with immediate RHS to SADDO by negating the immediate.
|
2019-04-09 18:33:56 +00:00 |
|
sub.ll
|
…
|
|
|
subcarry.ll
|
[DAGCombine] More diamong carry pattern optimization.
|
2019-07-03 16:15:59 +00:00 |
|
subreg-to-reg-0.ll
|
…
|
|
|
subreg-to-reg-1.ll
|
…
|
|
|
subreg-to-reg-2.ll
|
…
|
|
|
subreg-to-reg-3.ll
|
…
|
|
|
subreg-to-reg-4.ll
|
…
|
|
|
subreg-to-reg-6.ll
|
…
|
|
|
subvector-broadcast.ll
|
[x86] split 256-bit store of concatenated vectors
|
2019-06-04 16:40:04 +00:00 |
|
sunkaddr-ext.ll
|
…
|
|
|
swap.ll
|
Revert r357256 "[DAGCombine] Improve Lifetime node chains."
|
2019-04-03 07:41:58 +00:00 |
|
swift-error.ll
|
…
|
|
|
swift-return.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
swiftcc.ll
|
[X86] Enable tail calls for CallingConv::Swift
|
2019-04-05 20:18:25 +00:00 |
|
swifterror.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
swiftself.ll
|
[FastISel] Skip creating unnecessary vregs for arguments
|
2019-06-10 16:53:37 +00:00 |
|
switch-bt.ll
|
…
|
|
|
switch-crit-edge-constant.ll
|
…
|
|
|
switch-default-only.ll
|
…
|
|
|
switch-density.ll
|
…
|
|
|
switch-edge-weight.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
switch-jump-table.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
switch-lower-peel-top-case.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
switch-or.ll
|
…
|
|
|
switch-order-weight.ll
|
…
|
|
|
switch-zextload.ll
|
…
|
|
|
switch.ll
|
[test] Change comment wording (NFC)
|
2019-06-18 23:31:10 +00:00 |
|
swizzle-2.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
swizzle-avx2.ll
|
…
|
|
|
system-intrinsics-64-xsave.ll
|
…
|
|
|
system-intrinsics-64-xsavec.ll
|
…
|
|
|
system-intrinsics-64-xsaveopt.ll
|
…
|
|
|
system-intrinsics-64-xsaves.ll
|
…
|
|
|
system-intrinsics-64.ll
|
…
|
|
|
system-intrinsics-xgetbv.ll
|
…
|
|
|
system-intrinsics-xsave.ll
|
…
|
|
|
system-intrinsics-xsavec.ll
|
…
|
|
|
system-intrinsics-xsaveopt.ll
|
…
|
|
|
system-intrinsics-xsaves.ll
|
…
|
|
|
system-intrinsics-xsetbv.ll
|
…
|
|
|
system-intrinsics.ll
|
…
|
|
|
tail-call-attrs.ll
|
…
|
|
|
tail-call-casts.ll
|
…
|
|
|
tail-call-conditional.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
tail-call-got.ll
|
…
|
|
|
tail-call-legality.ll
|
…
|
|
|
tail-call-mutable-memarg.ll
|
…
|
|
|
tail-call-parameter-attrs-mismatch.ll
|
…
|
|
|
tail-call-win64.ll
|
…
|
|
|
tail-dup-addr.ll
|
…
|
|
|
tail-dup-catchret.ll
|
…
|
|
|
tail-dup-debugloc.ll
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
tail-dup-merge-loop-headers.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
tail-dup-no-other-successor.ll
|
…
|
|
|
tail-dup-repeat.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
tail-merge-after-mbp.mir
|
[Codegen] Merge tail blocks with no successors after block placement
|
2019-06-13 18:11:32 +00:00 |
|
tail-merge-debugloc.ll
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
tail-merge-identical.ll
|
…
|
|
|
tail-merge-unreachable.ll
|
…
|
|
|
tail-merge-wineh.ll
|
…
|
|
|
tail-opts.ll
|
[Codegen] Merge tail blocks with no successors after block placement
|
2019-06-13 18:11:32 +00:00 |
|
tail-threshold.ll
|
[Codegen] Merge tail blocks with no successors after block placement
|
2019-06-13 18:11:32 +00:00 |
|
tailcall-64.ll
|
…
|
|
|
tailcall-calleesave.ll
|
…
|
|
|
tailcall-cgp-dup.ll
|
[CGP] Look through bitcasts when duplicating returns for tail calls
|
2019-04-23 21:57:46 +00:00 |
|
tailcall-disable.ll
|
…
|
|
|
tailcall-fastisel.ll
|
…
|
|
|
tailcall-largecode.ll
|
…
|
|
|
tailcall-lifetime-end.ll
|
…
|
|
|
tailcall-mem-intrinsics.ll
|
…
|
|
|
tailcall-msvc-conventions.ll
|
…
|
|
|
tailcall-multiret.ll
|
…
|
|
|
tailcall-pseudo-64.mir
|
[X86] Preserve operand flag when expanding TCRETURNri
|
2019-04-05 20:18:21 +00:00 |
|
tailcall-pseudo.mir
|
[X86] Preserve operand flag when expanding TCRETURNri
|
2019-04-05 20:18:21 +00:00 |
|
tailcall-readnone.ll
|
…
|
|
|
tailcall-returndup-void.ll
|
…
|
|
|
tailcall-ri64.ll
|
…
|
|
|
tailcall-stackalign.ll
|
…
|
|
|
tailcall-structret.ll
|
…
|
|
|
tailcall.ll
|
…
|
|
|
tailcallbyval.ll
|
…
|
|
|
tailcallbyval64.ll
|
…
|
|
|
tailcallfp.ll
|
…
|
|
|
tailcallfp2.ll
|
…
|
|
|
tailcallpic1.ll
|
…
|
|
|
tailcallpic2.ll
|
…
|
|
|
tailcallpic3.ll
|
…
|
|
|
tailcallstack64.ll
|
…
|
|
|
taildup-crash.ll
|
Fixed typos in tests: s/CEHCK/CHECK/
|
2019-02-25 13:12:33 +00:00 |
|
tailjmp_gotpcrel_relax_relocation.ll
|
…
|
|
|
targetLoweringGeneric.ll
|
…
|
|
|
tbm-intrinsics-fast-isel-x86_64.ll
|
…
|
|
|
tbm-intrinsics-fast-isel.ll
|
…
|
|
|
tbm-intrinsics-x86_64.ll
|
…
|
|
|
tbm-intrinsics.ll
|
…
|
|
|
tbm_patterns.ll
|
[X86] Add patterns with and_flag_nocf for BLSI and TBM instructions.
|
2019-07-10 22:44:32 +00:00 |
|
test-nofold.ll
|
…
|
|
|
test-shrink-bug.ll
|
[Codegen] Merge tail blocks with no successors after block placement
|
2019-06-13 18:11:32 +00:00 |
|
test-shrink.ll
|
…
|
|
|
test-vs-bittest.ll
|
…
|
|
|
test_x86condbr_globaladdr.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
testb-je-fusion.ll
|
[X86] Make the post machine scheduler macrofusion-aware.
|
2019-04-03 09:37:30 +00:00 |
|
testl-commute.ll
|
…
|
|
|
this-return-64.ll
|
…
|
|
|
throws-cfi-fp.ll
|
…
|
|
|
throws-cfi-no-fp.ll
|
…
|
|
|
tls-addr-non-leaf-function.ll
|
…
|
|
|
tls-android-negative.ll
|
…
|
|
|
tls-android.ll
|
…
|
|
|
tls-local-dynamic.ll
|
…
|
|
|
tls-models.ll
|
…
|
|
|
tls-no-plt.ll
|
[X86] -fno-plt: use GOT __tls_get_addr only if GOTPCRELX is enabled
|
2019-07-11 10:10:09 +00:00 |
|
tls-pic.ll
|
…
|
|
|
tls-pie.ll
|
…
|
|
|
tls-shrink-wrapping.ll
|
…
|
|
|
tls-windows-itanium.ll
|
[llvm-readobj] Change -long-option to --long-option in tests. NFC
|
2019-05-01 05:27:20 +00:00 |
|
tls.ll
|
…
|
|
|
tlv-1.ll
|
…
|
|
|
tlv-2.ll
|
…
|
|
|
tlv-3.ll
|
…
|
|
|
token_landingpad.ll
|
…
|
|
|
trap.ll
|
…
|
|
|
tree_way_unsigned_cmp.ll
|
[NFC] Added test from PR19758
|
2019-06-09 15:12:46 +00:00 |
|
trunc-and.ll
|
[DAGCombiner] prevent infinite looping by truncating 'and' (PR40793)
|
2019-02-21 16:01:48 +00:00 |
|
trunc-ext-ld-st.ll
|
[DAGCombiner] loosen restrictions for moving shuffles after vector binop
|
2019-04-03 13:42:06 +00:00 |
|
trunc-store.ll
|
[X86] Avoid icmp undef in reduced tests
|
2019-03-13 18:36:59 +00:00 |
|
trunc-subvector.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
trunc-to-bool.ll
|
[X86] Don't set exception mask bits when modifying FPCW to change rounding mode for fp->int conversion
|
2019-02-15 21:59:33 +00:00 |
|
twoaddr-coalesce-2.ll
|
…
|
|
|
twoaddr-coalesce-3.ll
|
…
|
|
|
twoaddr-coalesce.ll
|
…
|
|
|
twoaddr-dbg-value.mir
|
…
|
|
|
twoaddr-lea.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
twoaddr-pass-sink.ll
|
…
|
|
|
twoaddr-sink-terminator.ll
|
…
|
|
|
uadd_sat.ll
|
[x86] improve the default expansion of uaddsat/usubsat
|
2019-03-24 13:55:54 +00:00 |
|
uadd_sat_vec.ll
|
[x86] narrow extract subvector of vector select
|
2019-06-07 13:17:46 +00:00 |
|
uint64-to-float.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
uint_to_fp-2.ll
|
…
|
|
|
uint_to_fp-3.ll
|
…
|
|
|
uint_to_fp.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
umul-with-carry.ll
|
…
|
|
|
umul-with-overflow.ll
|
[SDAG] Use shift amount type in MULO promotion; NFC
|
2019-02-19 17:37:55 +00:00 |
|
umul_fix.ll
|
Revert r356996 "[DAG] Avoid smart constructor-based dangling nodes."
|
2019-03-27 19:54:41 +00:00 |
|
umulo-64-legalisation-lowering.ll
|
…
|
|
|
umulo-128-legalisation-lowering.ll
|
…
|
|
|
unaligned-32-byte-memops.ll
|
…
|
|
|
unaligned-load.ll
|
…
|
|
|
unaligned-spill-folding.ll
|
…
|
|
|
undef-eflags.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
undef-globals-bss.ll
|
…
|
|
|
undef-label.ll
|
…
|
|
|
undef-ops.ll
|
[SelectionDAG] Add icmp UNDEF handling to SelectionDAG::FoldSetCC
|
2019-03-25 18:51:57 +00:00 |
|
unfold-masked-merge-scalar-constmask-innerouter.ll
|
[X86] Enable 8-bit OR with disjoint bits to convert to LEA
|
2019-03-05 18:37:33 +00:00 |
|
unfold-masked-merge-scalar-constmask-interleavedbits.ll
|
[X86] Enable 8-bit OR with disjoint bits to convert to LEA
|
2019-03-05 18:37:33 +00:00 |
|
unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
|
[X86] Enable 8-bit OR with disjoint bits to convert to LEA
|
2019-03-05 18:37:33 +00:00 |
|
unfold-masked-merge-scalar-constmask-lowhigh.ll
|
[X86] Enable 8-bit OR with disjoint bits to convert to LEA
|
2019-03-05 18:37:33 +00:00 |
|
unfold-masked-merge-scalar-variablemask.ll
|
[DAGCombine] Fold (x & ~y) | y patterns
|
2019-03-17 15:45:38 +00:00 |
|
unfold-masked-merge-vector-variablemask-const.ll
|
Revert r356996 "[DAG] Avoid smart constructor-based dangling nodes."
|
2019-03-27 19:54:41 +00:00 |
|
unfold-masked-merge-vector-variablemask.ll
|
…
|
|
|
unknown-location.ll
|
…
|
|
|
unreachable-loop-sinking.ll
|
…
|
|
|
unreachable-mbb-undef-phi.mir
|
…
|
|
|
unreachable-trap.ll
|
…
|
|
|
unreachableblockelim.ll
|
…
|
|
|
unused_stackslots.ll
|
…
|
|
|
unwind-init.ll
|
…
|
|
|
unwindraise.ll
|
…
|
|
|
update-terminator-debugloc.ll
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
update-terminator.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
urem-i8-constant.ll
|
…
|
|
|
urem-power-of-two.ll
|
…
|
|
|
urem-seteq-optsize.ll
|
[CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 3)
|
2019-06-27 21:52:10 +00:00 |
|
urem-seteq-vec-nonsplat.ll
|
[NFC][Codegen] Revisit test coverage for X % C == 0 fold once more (add tests with '1' divisor)
|
2019-06-28 17:26:28 +00:00 |
|
urem-seteq-vec-splat.ll
|
[NFC][Codegen] Revisit test coverage for X % C == 0 fold once more (add tests with '1' divisor)
|
2019-06-28 17:26:28 +00:00 |
|
urem-seteq.ll
|
[NFC][Codegen] Revisit test coverage for X % C == 0 fold
|
2019-06-28 11:36:34 +00:00 |
|
use-add-flags.ll
|
…
|
|
|
usub_sat.ll
|
[x86] improve the default expansion of uaddsat/usubsat
|
2019-03-24 13:55:54 +00:00 |
|
usub_sat_vec.ll
|
[x86] narrow extract subvector of vector select
|
2019-06-07 13:17:46 +00:00 |
|
utf8.ll
|
…
|
|
|
utf16-cfstrings.ll
|
…
|
|
|
uwtables.ll
|
…
|
|
|
v2f32.ll
|
…
|
|
|
v4f32-immediate.ll
|
…
|
|
|
v4i32load-crash.ll
|
…
|
|
|
v8i1-masks.ll
|
…
|
|
|
vaargs.ll
|
…
|
|
|
vaes-intrinsics-avx-x86.ll
|
…
|
|
|
vaes-intrinsics-avx512-x86.ll
|
…
|
|
|
vaes-intrinsics-avx512vl-x86.ll
|
…
|
|
|
var-permute-128.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
|
var-permute-256.ll
|
[X86][SSE] Fold extract_subvector(vselect(x,y,z),0) -> vselect(extract_subvector(x,0),extract_subvector(y,0),extract_subvector(z,0))
|
2019-06-22 17:57:01 +00:00 |
|
var-permute-512.ll
|
…
|
|
|
vararg-callee-cleanup.ll
|
…
|
|
|
vararg_no_start.ll
|
…
|
|
|
vararg_tailcall.ll
|
…
|
|
|
variable-sized-darwin-bzero.ll
|
…
|
|
|
variadic-node-pic.ll
|
…
|
|
|
vastart-defs-eflags.ll
|
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
|
2019-03-13 17:07:09 +00:00 |
|
vbinop-simplify-bug.ll
|
…
|
|
|
vec-copysign-avx512.ll
|
…
|
|
|
vec-copysign.ll
|
…
|
|
|
vec-libcalls.ll
|
…
|
|
|
vec-loadsingles-alignment.ll
|
…
|
|
|
vec-trunc-store.ll
|
…
|
|
|
vec3.ll
|
…
|
|
|
vec_align.ll
|
…
|
|
|
vec_align_i256.ll
|
…
|
|
|
vec_anyext.ll
|
…
|
|
|
vec_call.ll
|
…
|
|
|
vec_cast.ll
|
…
|
|
|
vec_cast2.ll
|
…
|
|
|
vec_cast3.ll
|
[X86] In FP_TO_INTHelper, when moving data from SSE register to X87 register file via the stack, use the same stack slot we use for the integer conversion.
|
2019-02-17 19:23:49 +00:00 |
|
vec_clz.ll
|
[CodeGen] Add missing vector type legalization for ctlz_zero_undef
|
2019-06-24 19:27:07 +00:00 |
|
vec_cmp_sint-128.ll
|
…
|
|
|
vec_cmp_uint-128.ll
|
…
|
|
|
vec_compare-sse4.ll
|
…
|
|
|
vec_compare.ll
|
…
|
|
|
vec_ctbits.ll
|
…
|
|
|
vec_ext_inreg.ll
|
…
|
|
|
vec_extract-avx.ll
|
[X86] Add DAG combine to turn (vzmovl (insert_subvector undef, X, 0)) into (insert_subvector allzeros, (vzmovl X), 0)
|
2019-06-21 19:10:21 +00:00 |
|
vec_extract-mmx.ll
|
[DAGCombine] Prune unnused nodes.
|
2019-03-29 17:35:56 +00:00 |
|
vec_extract-sse4.ll
|
…
|
|
|
vec_extract.ll
|
[X86][SSE] LowerINSERT_VECTOR_ELT - early out for out of range indices
|
2019-07-05 10:34:53 +00:00 |
|
vec_fabs.ll
|
…
|
|
|
vec_floor.ll
|
[X86][InstCombine] Remove InstCombine code that turns X86 round intrinsics into llvm.ceil/floor. Remove some isel patterns that existed because that was happening.
|
2019-05-22 20:04:55 +00:00 |
|
vec_fneg.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to some X86/ and XCore/ tests."
|
2019-06-13 19:24:51 +00:00 |
|
vec_fp_to_int-widen.ll
|
[X86] Correct v4f32->v2i64 cvt(t)ps2(u)qq memory isel patterns
|
2019-07-01 19:01:37 +00:00 |
|
vec_fp_to_int.ll
|
[X86] Correct v4f32->v2i64 cvt(t)ps2(u)qq memory isel patterns
|
2019-07-01 19:01:37 +00:00 |
|
vec_fpext.ll
|
[X86] Remove avx512 isel patterns for fpextend+load. Prefer to only match fp extloads instead.
|
2019-05-31 06:21:53 +00:00 |
|
vec_fptrunc.ll
|
[x86] split 256-bit store of concatenated vectors
|
2019-06-04 16:40:04 +00:00 |
|
vec_i64.ll
|
…
|
|
|
vec_ins_extract-1.ll
|
…
|
|
|
vec_ins_extract.ll
|
…
|
|
|
vec_insert-2.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
|
vec_insert-3.ll
|
…
|
|
|
vec_insert-4.ll
|
…
|
|
|
vec_insert-5.ll
|
[X86][SSE] Fold scalar_to_vector(i64 anyext(x)) -> bitcast(scalar_to_vector(i32 anyext(x)))
|
2019-03-15 19:14:28 +00:00 |
|
vec_insert-7.ll
|
[DAGCombiner][X86][SystemZ][AArch64] Combine some cases of (bitcast (build_vector constants)) between legalize types and legalize dag.
|
2019-03-04 19:12:16 +00:00 |
|
vec_insert-8.ll
|
…
|
|
|
vec_insert-9.ll
|
…
|
|
|
vec_insert-mmx.ll
|
…
|
|
|
vec_int_to_fp-widen.ll
|
[X86] Add a DAG combine to replace vector loads feeding a v4i32->v2f64 CVTSI2FP/CVTUI2FP node with a vzload.
|
2019-07-01 07:09:31 +00:00 |
|
vec_int_to_fp.ll
|
[X86] Add a DAG combine to replace vector loads feeding a v4i32->v2f64 CVTSI2FP/CVTUI2FP node with a vzload.
|
2019-07-01 07:09:31 +00:00 |
|
vec_loadsingles.ll
|
…
|
|
|
vec_logical.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to some X86/ and XCore/ tests."
|
2019-06-13 19:24:51 +00:00 |
|
vec_minmax_match.ll
|
…
|
|
|
vec_minmax_sint.ll
|
Revert r356996 "[DAG] Avoid smart constructor-based dangling nodes."
|
2019-03-27 19:54:41 +00:00 |
|
vec_minmax_uint.ll
|
Revert r356996 "[DAG] Avoid smart constructor-based dangling nodes."
|
2019-03-27 19:54:41 +00:00 |
|
vec_partial.ll
|
…
|
|
|
vec_reassociate.ll
|
…
|
|
|
vec_return.ll
|
…
|
|
|
vec_round.ll
|
…
|
|
|
vec_saddo.ll
|
[DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support
|
2019-07-11 14:45:03 +00:00 |
|
vec_sdiv_to_shift.ll
|
…
|
|
|
vec_set-2.ll
|
…
|
|
|
vec_set-3.ll
|
…
|
|
|
vec_set-4.ll
|
…
|
|
|
vec_set-6.ll
|
…
|
|
|
vec_set-7.ll
|
…
|
|
|
vec_set-8.ll
|
…
|
|
|
vec_set-A.ll
|
…
|
|
|
vec_set-B.ll
|
…
|
|
|
vec_set-C.ll
|
…
|
|
|
vec_set-D.ll
|
…
|
|
|
vec_set-F.ll
|
…
|
|
|
vec_set-H.ll
|
…
|
|
|
vec_set.ll
|
…
|
|
|
vec_setcc-2.ll
|
[x86] use psubus for more vsetcc lowering (PR39859)
|
2019-04-23 15:20:17 +00:00 |
|
vec_setcc.ll
|
…
|
|
|
vec_shift.ll
|
…
|
|
|
vec_shift2.ll
|
[X86][SSE] Attempt to convert SSE shift-by-var to shift-by-imm.
|
2019-03-15 11:05:42 +00:00 |
|
vec_shift3.ll
|
…
|
|
|
vec_shift4.ll
|
…
|
|
|
vec_shift5.ll
|
…
|
|
|
vec_shift6.ll
|
…
|
|
|
vec_shift7.ll
|
…
|
|
|
vec_shuf-insert.ll
|
…
|
|
|
vec_smulo.ll
|
[x86] split 256-bit store of concatenated vectors
|
2019-06-04 16:40:04 +00:00 |
|
vec_split.ll
|
…
|
|
|
vec_ss_load_fold.ll
|
…
|
|
|
vec_ssubo.ll
|
[DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support
|
2019-07-11 14:45:03 +00:00 |
|
vec_trunc_sext.ll
|
…
|
|
|
vec_uaddo.ll
|
[x86] split 256-bit store of concatenated vectors
|
2019-06-04 16:40:04 +00:00 |
|
vec_udiv_to_shift.ll
|
…
|
|
|
vec_uint_to_fp-fastmath.ll
|
…
|
|
|
vec_uint_to_fp.ll
|
…
|
|
|
vec_umulo.ll
|
[x86] split 256-bit store of concatenated vectors
|
2019-06-04 16:40:04 +00:00 |
|
vec_unsafe-fp-math.ll
|
…
|
|
|
vec_usubo.ll
|
[x86] split 256-bit store of concatenated vectors
|
2019-06-04 16:40:04 +00:00 |
|
vec_zero-2.ll
|
…
|
|
|
vec_zero.ll
|
[X86][SSE] Regenerate vector zero tests
|
2019-03-05 16:52:14 +00:00 |
|
vec_zero_cse.ll
|
[DAGCombiner][X86][SystemZ][AArch64] Combine some cases of (bitcast (build_vector constants)) between legalize types and legalize dag.
|
2019-03-04 19:12:16 +00:00 |
|
vecloadextract.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
vector-bitreverse.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
vector-blend.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
vector-compare-all_of.ll
|
[X86][SSE] Fold movmsk(not(x)) -> not(movmsk)
|
2019-05-17 17:56:25 +00:00 |
|
vector-compare-any_of.ll
|
[X86][SSE] Fold movmsk(not(x)) -> not(movmsk)
|
2019-05-17 17:56:25 +00:00 |
|
vector-compare-combines.ll
|
…
|
|
|
vector-compare-results.ll
|
…
|
|
|
vector-compare-simplify.ll
|
…
|
|
|
vector-constrained-fp-intrinsics-fma.ll
|
…
|
|
|
vector-constrained-fp-intrinsics.ll
|
Add constrained fptrunc and fpext intrinsics.
|
2019-05-13 13:23:30 +00:00 |
|
vector-ext-logic.ll
|
[DAG] Refactor DAGCombiner::ReassociateOps
|
2019-04-29 17:50:10 +00:00 |
|
vector-extend-inreg.ll
|
[X86] Use vmovq for v4i64/v4f64/v8i64/v8f64 vzmovl.
|
2019-06-21 17:24:21 +00:00 |
|
vector-fshl-128.ll
|
[TargetLowering] SimplifyDemandedVectorElts - add shift/rotate support.
|
2019-06-27 14:25:54 +00:00 |
|
vector-fshl-256.ll
|
[TargetLowering] SimplifyDemandedVectorElts - add shift/rotate support.
|
2019-06-27 14:25:54 +00:00 |
|
vector-fshl-512.ll
|
[TargetLowering] SimplifyDemandedVectorElts - add shift/rotate support.
|
2019-06-27 14:25:54 +00:00 |
|
vector-fshl-rot-128.ll
|
…
|
|
|
vector-fshl-rot-256.ll
|
[DAGCombiner] try to move bitcast after extract_subvector
|
2019-05-12 14:43:20 +00:00 |
|
vector-fshl-rot-512.ll
|
[X86][SSE] Add SSE vector shift support to SimplifyDemandedVectorEltsForTargetNode vector splitting
|
2019-05-01 13:51:09 +00:00 |
|
vector-fshr-128.ll
|
[TargetLowering] SimplifyDemandedVectorElts - add shift/rotate support.
|
2019-06-27 14:25:54 +00:00 |
|
vector-fshr-256.ll
|
[TargetLowering] SimplifyDemandedVectorElts - add shift/rotate support.
|
2019-06-27 14:25:54 +00:00 |
|
vector-fshr-512.ll
|
[TargetLowering] SimplifyDemandedVectorElts - add shift/rotate support.
|
2019-06-27 14:25:54 +00:00 |
|
vector-fshr-rot-128.ll
|
…
|
|
|
vector-fshr-rot-256.ll
|
[DAGCombiner] try to move bitcast after extract_subvector
|
2019-05-12 14:43:20 +00:00 |
|
vector-fshr-rot-512.ll
|
[X86][SSE] Add SSE vector shift support to SimplifyDemandedVectorEltsForTargetNode vector splitting
|
2019-05-01 13:51:09 +00:00 |
|
vector-gep.ll
|
[x86] split 256-bit store of concatenated vectors
|
2019-06-04 16:40:04 +00:00 |
|
vector-half-conversions.ll
|
[SelectionDAG][X86] Use stack load/store in PromoteIntRes_BITCAST when the input needs to be be split and the output type is a vector.
|
2019-04-25 18:19:59 +00:00 |
|
vector-idiv-sdiv-128.ll
|
[DAGCombiner][X86][AArch64] (x - C) + y -> (x + y) - C fold. Try 2
|
2019-05-30 20:37:49 +00:00 |
|
vector-idiv-sdiv-256.ll
|
[DAGCombiner][X86][AArch64] (x - C) + y -> (x + y) - C fold. Try 2
|
2019-05-30 20:37:49 +00:00 |
|
vector-idiv-sdiv-512.ll
|
[DAGCombiner][X86][AArch64] (x - C) + y -> (x + y) - C fold. Try 2
|
2019-05-30 20:37:49 +00:00 |
|
vector-idiv-udiv-128.ll
|
[X86] lowerBuildVectorToBitOp - support build_vector(shift()) -> shift(build_vector(),C)
|
2019-05-25 18:02:17 +00:00 |
|
vector-idiv-udiv-256.ll
|
[X86] lowerBuildVectorToBitOp - support build_vector(shift()) -> shift(build_vector(),C)
|
2019-05-25 18:02:17 +00:00 |
|
vector-idiv-udiv-512.ll
|
[X86] lowerBuildVectorToBitOp - support build_vector(shift()) -> shift(build_vector(),C)
|
2019-05-25 18:02:17 +00:00 |
|
vector-idiv-v2i32.ll
|
[X86][SSE] Attempt to convert SSE shift-by-var to shift-by-imm.
|
2019-03-15 11:05:42 +00:00 |
|
vector-idiv.ll
|
…
|
|
|
vector-interleave.ll
|
…
|
|
|
vector-intrinsics.ll
|
…
|
|
|
vector-lzcnt-128.ll
|
…
|
|
|
vector-lzcnt-256.ll
|
…
|
|
|
vector-lzcnt-512.ll
|
[X86][AVX] isNOT - add extract_subvector(xor X, -1) -> extract_subvector(X) fold.
|
2019-05-17 14:04:56 +00:00 |
|
vector-merge-store-fp-constants.ll
|
…
|
|
|
vector-mul.ll
|
[SelectionDAG] Add SimplifyDemandedBits handling for ISD::SCALAR_TO_VECTOR
|
2019-03-15 17:00:55 +00:00 |
|
vector-narrow-binop.ll
|
[DAGCombiner] narrow vector binop with inserts/extract
|
2019-05-13 14:31:14 +00:00 |
|
vector-partial-undef.ll
|
…
|
|
|
vector-pcmp.ll
|
[SelectionDAG] computeKnownBits - support constant pool values from target
|
2019-05-24 10:03:11 +00:00 |
|
vector-popcnt-128.ll
|
…
|
|
|
vector-popcnt-256.ll
|
…
|
|
|
vector-popcnt-512.ll
|
…
|
|
|
vector-reduce-add-widen.ll
|
Improve reduction intrinsics by overloading result value.
|
2019-06-13 09:37:38 +00:00 |
|
vector-reduce-add.ll
|
Improve reduction intrinsics by overloading result value.
|
2019-06-13 09:37:38 +00:00 |
|
vector-reduce-and-bool.ll
|
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
|
2019-06-25 10:51:15 +00:00 |
|
vector-reduce-and-widen.ll
|
Improve reduction intrinsics by overloading result value.
|
2019-06-13 09:37:38 +00:00 |
|
vector-reduce-and.ll
|
Improve reduction intrinsics by overloading result value.
|
2019-06-13 09:37:38 +00:00 |
|
vector-reduce-fadd-fast.ll
|
[X86] Regenerate fast fadd reduction tests. NFCI
|
2019-06-24 16:25:30 +00:00 |
|
vector-reduce-fadd.ll
|
Change semantics of fadd/fmul vector reductions.
|
2019-06-11 08:22:10 +00:00 |
|
vector-reduce-fmax-nnan.ll
|
Improve reduction intrinsics by overloading result value.
|
2019-06-13 09:37:38 +00:00 |
|
vector-reduce-fmax.ll
|
Improve reduction intrinsics by overloading result value.
|
2019-06-13 09:37:38 +00:00 |
|
vector-reduce-fmin-nnan.ll
|
Improve reduction intrinsics by overloading result value.
|
2019-06-13 09:37:38 +00:00 |
|
vector-reduce-fmin.ll
|
Improve reduction intrinsics by overloading result value.
|
2019-06-13 09:37:38 +00:00 |
|
vector-reduce-fmul-fast.ll
|
Change semantics of fadd/fmul vector reductions.
|
2019-06-11 08:22:10 +00:00 |
|
vector-reduce-fmul.ll
|
Change semantics of fadd/fmul vector reductions.
|
2019-06-11 08:22:10 +00:00 |
|
vector-reduce-mul-widen.ll
|
[X86][AVX] combineExtractSubvector - 'little to big' extract_subvector(bitcast()) support
|
2019-06-26 11:21:09 +00:00 |
|
vector-reduce-mul.ll
|
[X86][AVX] combineExtractSubvector - 'little to big' extract_subvector(bitcast()) support
|
2019-06-26 11:21:09 +00:00 |
|
vector-reduce-or-bool.ll
|
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
|
2019-06-25 10:51:15 +00:00 |
|
vector-reduce-or-widen.ll
|
Improve reduction intrinsics by overloading result value.
|
2019-06-13 09:37:38 +00:00 |
|
vector-reduce-or.ll
|
Improve reduction intrinsics by overloading result value.
|
2019-06-13 09:37:38 +00:00 |
|
vector-reduce-smax-widen.ll
|
[X86][SSE] X86TargetLowering::isBinOp - add PCMPGT
|
2019-06-26 14:34:41 +00:00 |
|
vector-reduce-smax.ll
|
[X86] ComputeNumSignBitsForTargetNode - add target shuffle support.
|
2019-07-03 17:06:59 +00:00 |
|
vector-reduce-smin-widen.ll
|
[X86][SSE] X86TargetLowering::isBinOp - add PCMPGT
|
2019-06-26 14:34:41 +00:00 |
|
vector-reduce-smin.ll
|
[X86] ComputeNumSignBitsForTargetNode - add target shuffle support.
|
2019-07-03 17:06:59 +00:00 |
|
vector-reduce-umax-widen.ll
|
[X86][SSE] X86TargetLowering::isBinOp - add PCMPGT
|
2019-06-26 14:34:41 +00:00 |
|
vector-reduce-umax.ll
|
[X86][SSE] X86TargetLowering::isBinOp - add PCMPGT
|
2019-06-26 14:34:41 +00:00 |
|
vector-reduce-umin-widen.ll
|
[X86][SSE] X86TargetLowering::isBinOp - add PCMPGT
|
2019-06-26 14:34:41 +00:00 |
|
vector-reduce-umin.ll
|
[X86][SSE] X86TargetLowering::isBinOp - add PCMPGT
|
2019-06-26 14:34:41 +00:00 |
|
vector-reduce-xor-bool.ll
|
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
|
2019-06-25 10:51:15 +00:00 |
|
vector-reduce-xor-widen.ll
|
Improve reduction intrinsics by overloading result value.
|
2019-06-13 09:37:38 +00:00 |
|
vector-reduce-xor.ll
|
Improve reduction intrinsics by overloading result value.
|
2019-06-13 09:37:38 +00:00 |
|
vector-rem.ll
|
…
|
|
|
vector-rotate-128.ll
|
…
|
|
|
vector-rotate-256.ll
|
[DAGCombiner] try to move bitcast after extract_subvector
|
2019-05-12 14:43:20 +00:00 |
|
vector-rotate-512.ll
|
[X86][SSE] Add SSE vector shift support to SimplifyDemandedVectorEltsForTargetNode vector splitting
|
2019-05-01 13:51:09 +00:00 |
|
vector-sext-widen.ll
|
[X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(concat_vectors(x,y),c)
|
2019-07-04 10:17:10 +00:00 |
|
vector-sext.ll
|
[X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(concat_vectors(x,y),c)
|
2019-07-04 10:17:10 +00:00 |
|
vector-shift-ashr-128.ll
|
…
|
|
|
vector-shift-ashr-256.ll
|
[DAGCombiner] try to move bitcast after extract_subvector
|
2019-05-12 14:43:20 +00:00 |
|
vector-shift-ashr-512.ll
|
[X86][SSE] Add SSE vector shift support to SimplifyDemandedVectorEltsForTargetNode vector splitting
|
2019-05-01 13:51:09 +00:00 |
|
vector-shift-ashr-sub128-widen.ll
|
[SelectionDAG] Add icmp UNDEF handling to SelectionDAG::FoldSetCC
|
2019-03-25 18:51:57 +00:00 |
|
vector-shift-ashr-sub128.ll
|
[X86] Make movsd commutable to shufpd with a 0x02 immediate on pre-SSE4.1 targets.
|
2019-07-08 06:52:43 +00:00 |
|
vector-shift-by-select-loop.ll
|
[CodeGenPrepare][x86] shift both sides of a vector select when profitable
|
2019-06-16 15:29:03 +00:00 |
|
vector-shift-lshr-128.ll
|
[CodeGenPrepare][x86] shift both sides of a vector select when profitable
|
2019-06-16 15:29:03 +00:00 |
|
vector-shift-lshr-256.ll
|
[X86][SSE] Add SSE vector shift support to SimplifyDemandedVectorEltsForTargetNode vector splitting
|
2019-05-01 13:51:09 +00:00 |
|
vector-shift-lshr-512.ll
|
[X86][SSE] Add SSE vector shift support to SimplifyDemandedVectorEltsForTargetNode vector splitting
|
2019-05-01 13:51:09 +00:00 |
|
vector-shift-lshr-sub128-widen.ll
|
[SelectionDAG] Add icmp UNDEF handling to SelectionDAG::FoldSetCC
|
2019-03-25 18:51:57 +00:00 |
|
vector-shift-lshr-sub128.ll
|
[SelectionDAG] computeKnownBits - support constant pool values from target
|
2019-05-24 10:03:11 +00:00 |
|
vector-shift-shl-128.ll
|
[x86] move vector shift tests for PR37428; NFC
|
2019-06-14 15:23:09 +00:00 |
|
vector-shift-shl-256.ll
|
[X86][SSE] Add SSE vector shift support to SimplifyDemandedVectorEltsForTargetNode vector splitting
|
2019-05-01 13:51:09 +00:00 |
|
vector-shift-shl-512.ll
|
[X86][SSE] Add SSE vector shift support to SimplifyDemandedVectorEltsForTargetNode vector splitting
|
2019-05-01 13:51:09 +00:00 |
|
vector-shift-shl-sub128-widen.ll
|
…
|
|
|
vector-shift-shl-sub128.ll
|
Revert rL356864 : [X86][SSE41] Start shuffle combining from ZERO_EXTEND_VECTOR_INREG (PR40685)
|
2019-03-27 10:25:02 +00:00 |
|
vector-shuffle-128-unpck.ll
|
[x86] prevent infinite looping from inverse shuffle transforms
|
2019-03-08 19:20:28 +00:00 |
|
vector-shuffle-128-v2.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
vector-shuffle-128-v4.ll
|
[X86][AMDGPU][DAGCombiner] Move call to allowsMemoryAccess into isLoadBitCastBeneficial/isStoreBitCastBeneficial to allow X86 to bypass it
|
2019-07-09 19:55:28 +00:00 |
|
vector-shuffle-128-v8.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
vector-shuffle-128-v16.ll
|
[X86] Rework the logic in LowerBuildVectorv16i8 to make better use of any_extend and break false dependencies. Other improvements
|
2019-06-26 20:16:19 +00:00 |
|
vector-shuffle-256-v4.ll
|
[X86][AVX] Add PR34359 shuffle test case.
|
2019-07-12 17:42:32 +00:00 |
|
vector-shuffle-256-v8.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
|
vector-shuffle-256-v16.ll
|
[X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(concat_vectors(x,y),c)
|
2019-07-04 10:17:10 +00:00 |
|
vector-shuffle-256-v32.ll
|
[X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(concat_vectors(x,y),c)
|
2019-07-04 10:17:10 +00:00 |
|
vector-shuffle-512-v8.ll
|
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
|
2019-06-25 10:51:15 +00:00 |
|
vector-shuffle-512-v16.ll
|
[X86][AVX] combineX86ShufflesRecursively - peek through extract_subvector
|
2019-07-03 15:46:08 +00:00 |
|
vector-shuffle-512-v32.ll
|
[X86][AVX] SimplifyDemandedVectorElts - combine PERMPD(x) -> EXTRACTF128(X)
|
2019-06-27 11:16:03 +00:00 |
|
vector-shuffle-512-v64.ll
|
[X86][AVX] Combine non-lane crossing binary shuffles using X86ISD::VPERMV3
|
2019-04-28 14:31:01 +00:00 |
|
vector-shuffle-avx512.ll
|
…
|
|
|
vector-shuffle-combining-avx.ll
|
[X86][AVX] Decode constant bits from insert_subvector(c1, c2, c3)
|
2019-06-15 17:05:24 +00:00 |
|
vector-shuffle-combining-avx2.ll
|
[X86] Use vmovq for v4i64/v4f64/v8i64/v8f64 vzmovl.
|
2019-06-21 17:24:21 +00:00 |
|
vector-shuffle-combining-avx512bw.ll
|
[X86][AVX] Decode constant bits from insert_subvector(c1, c2, c3)
|
2019-06-15 17:05:24 +00:00 |
|
vector-shuffle-combining-avx512bwvl.ll
|
…
|
|
|
vector-shuffle-combining-avx512vbmi.ll
|
[X86][AVX] Combine non-lane crossing binary shuffles using X86ISD::VPERMV3
|
2019-04-28 14:31:01 +00:00 |
|
vector-shuffle-combining-sse4a.ll
|
…
|
|
|
vector-shuffle-combining-sse41.ll
|
…
|
|
|
vector-shuffle-combining-ssse3.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
vector-shuffle-combining-xop.ll
|
[X86][AVX] Decode constant bits from insert_subvector(c1, c2, c3)
|
2019-06-15 17:05:24 +00:00 |
|
vector-shuffle-combining.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
vector-shuffle-masked.ll
|
…
|
|
|
vector-shuffle-mmx.ll
|
…
|
|
|
vector-shuffle-sse1.ll
|
[X86] Separate the memory size of vzext_load/vextract_store from the element size of the result type. Use them improve the codegen of v2f32 loads/stores with sse1 only.
|
2019-07-15 02:02:31 +00:00 |
|
vector-shuffle-sse4a.ll
|
…
|
|
|
vector-shuffle-sse41.ll
|
…
|
|
|
vector-shuffle-v1.ll
|
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
|
2019-06-25 10:51:15 +00:00 |
|
vector-shuffle-v48.ll
|
[X86][SSE] Regenerate v48 shuffle test on a variety of targets
|
2019-06-27 11:22:23 +00:00 |
|
vector-shuffle-variable-128.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
|
vector-shuffle-variable-256.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
|
vector-sqrt.ll
|
…
|
|
|
vector-trunc-math-widen.ll
|
[X86] combineVectorTruncationWithPACKUS - remove split/concatenation of mask
|
2019-04-18 17:23:09 +00:00 |
|
vector-trunc-math.ll
|
[X86] combineVectorTruncationWithPACKUS - remove split/concatenation of mask
|
2019-04-18 17:23:09 +00:00 |
|
vector-trunc-packus-widen.ll
|
[x86] narrow extract subvector of vector select
|
2019-06-07 13:17:46 +00:00 |
|
vector-trunc-packus.ll
|
[x86] narrow extract subvector of vector select
|
2019-06-07 13:17:46 +00:00 |
|
vector-trunc-ssat-widen.ll
|
[x86] narrow extract subvector of vector select
|
2019-06-07 13:17:46 +00:00 |
|
vector-trunc-ssat.ll
|
[x86] narrow extract subvector of vector select
|
2019-06-07 13:17:46 +00:00 |
|
vector-trunc-usat-widen.ll
|
[x86] narrow extract subvector of vector select
|
2019-06-07 13:17:46 +00:00 |
|
vector-trunc-usat.ll
|
[x86] narrow extract subvector of vector select
|
2019-06-07 13:17:46 +00:00 |
|
vector-trunc-widen.ll
|
[X86] Turn v16i16->v16i8 truncate+store into a any_extend+truncstore if we avx512f, but not avx512bw.
|
2019-06-23 23:51:21 +00:00 |
|
vector-trunc.ll
|
[X86] Turn v16i16->v16i8 truncate+store into a any_extend+truncstore if we avx512f, but not avx512bw.
|
2019-06-23 23:51:21 +00:00 |
|
vector-truncate-combine.ll
|
…
|
|
|
vector-tzcnt-128.ll
|
…
|
|
|
vector-tzcnt-256.ll
|
…
|
|
|
vector-tzcnt-512.ll
|
…
|
|
|
vector-unsigned-cmp.ll
|
…
|
|
|
vector-variable-idx.ll
|
…
|
|
|
vector-variable-idx2.ll
|
…
|
|
|
vector-width-store-merge.ll
|
Make sure that the DAG combiner doesn't merge stores that we explicitly
|
2019-05-07 19:25:34 +00:00 |
|
vector-zext-widen.ll
|
[X86] Copy test cases from vector-zext.ll to vector-zext-widen.ll. Same for vector-sext.ll. NFC
|
2019-07-02 18:39:59 +00:00 |
|
vector-zext.ll
|
[SelectionDAG] computeKnownBits - support constant pool values from target
|
2019-05-24 10:03:11 +00:00 |
|
vector-zmov.ll
|
[X86] Add a DAG combine to turn vzmovl+load into vzload if the load isn't volatile. Remove isel patterns for vzmovl+load
|
2019-06-25 17:08:26 +00:00 |
|
vector.ll
|
…
|
|
|
vector_splat-const-shift-of-constmasked.ll
|
[NFC][CodeGen][X86][AArch64] Add and-const-mask + const-shift pattern tests
|
2019-05-14 20:17:04 +00:00 |
|
vectorcall.ll
|
…
|
|
|
version_directive.ll
|
…
|
|
|
vfcmp.ll
|
…
|
|
|
viabs.ll
|
…
|
|
|
virtreg-physreg-def-regallocfast.mir
|
[RegAllocFast] Scan physcial reg definitions before assigning virtual reg definitions
|
2019-05-08 18:30:26 +00:00 |
|
virtual-registers-cleared-in-machine-functions-liveins.ll
|
…
|
|
|
visibility.ll
|
…
|
|
|
visibility2.ll
|
…
|
|
|
vmaskmov-offset.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
vmovq.ll
|
…
|
|
|
volatile-memstores-nooverlapping-load-stores.ll
|
Fixing @llvm.memcpy not honoring volatile.
|
2019-07-09 09:53:36 +00:00 |
|
volatile.ll
|
…
|
|
|
vortex-bug.ll
|
…
|
|
|
vp2intersect_multiple_pairs.ll
|
[X86] Correct the ins operand order for MASKPAIR16STORE to match other store instructions.
|
2019-05-31 05:20:27 +00:00 |
|
vpshufbitqbm-intrinsics-upgrade.ll
|
…
|
|
|
vpshufbitqbm-intrinsics.ll
|
…
|
|
|
vsel-cmp-load.ll
|
Revert r356996 "[DAG] Avoid smart constructor-based dangling nodes."
|
2019-03-27 19:54:41 +00:00 |
|
vselect-2.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
vselect-avx.ll
|
[x86] split 256-bit vector selects if operands are vector concats
|
2019-06-16 14:04:49 +00:00 |
|
vselect-constants.ll
|
…
|
|
|
vselect-minmax.ll
|
…
|
|
|
vselect-packss.ll
|
…
|
|
|
vselect-pcmp.ll
|
…
|
|
|
vselect-zero.ll
|
…
|
|
|
vselect.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
vshift-1.ll
|
…
|
|
|
vshift-2.ll
|
…
|
|
|
vshift-3.ll
|
…
|
|
|
vshift-4.ll
|
…
|
|
|
vshift-5.ll
|
…
|
|
|
vshift-6.ll
|
…
|
|
|
vshift_scalar.ll
|
…
|
|
|
vshift_split.ll
|
…
|
|
|
vshift_split2.ll
|
…
|
|
|
vsplit-and.ll
|
…
|
|
|
vzero-excess.ll
|
…
|
|
|
waitpkg-intrinsics.ll
|
…
|
|
|
warn-stack.ll
|
…
|
|
|
wbinvd-intrinsic.ll
|
…
|
|
|
wbnoinvd-intrinsic.ll
|
…
|
|
|
weak-undef.ll
|
…
|
|
|
weak.ll
|
…
|
|
|
weak_def_can_be_hidden.ll
|
…
|
|
|
webkit-jscc.ll
|
…
|
|
|
wide-fma-contraction.ll
|
…
|
|
|
wide-integer-cmp.ll
|
…
|
|
|
wide-integer-fold.ll
|
…
|
|
|
widen_arith-1.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
widen_arith-2.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
widen_arith-3.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
widen_arith-4.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
widen_arith-5.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
widen_arith-6.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
widen_bitops-0.ll
|
…
|
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|
widen_bitops-1.ll
|
…
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|
|
widen_cast-1.ll
|
[DAGCombiner][X86][SystemZ][AArch64] Combine some cases of (bitcast (build_vector constants)) between legalize types and legalize dag.
|
2019-03-04 19:12:16 +00:00 |
|
widen_cast-2.ll
|
[LegalizeVectorTypes] Allow single loads and stores for more short vectors
|
2019-03-27 20:35:56 +00:00 |
|
widen_cast-3.ll
|
[LegalizeVectorTypes] Allow single loads and stores for more short vectors
|
2019-03-27 20:35:56 +00:00 |
|
widen_cast-4.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
widen_cast-5.ll
|
…
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widen_cast-6.ll
|
…
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|
widen_compare-1.ll
|
[DAG] Move integer setcc %x, %x folding into FoldSetCC
|
2019-03-13 11:08:57 +00:00 |
|
widen_conv-1.ll
|
…
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widen_conv-2.ll
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…
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widen_conv-3.ll
|
[X86] Rework the logic in LowerBuildVectorv16i8 to make better use of any_extend and break false dependencies. Other improvements
|
2019-06-26 20:16:19 +00:00 |
|
widen_conv-4.ll
|
[X86][SSE] Fold scalar_to_vector(i64 anyext(x)) -> bitcast(scalar_to_vector(i32 anyext(x)))
|
2019-03-15 19:14:28 +00:00 |
|
widen_conversions.ll
|
…
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widen_extract-1.ll
|
…
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widen_load-0.ll
|
…
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widen_load-1.ll
|
…
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|
widen_load-2.ll
|
[TargetLowering] SimplifyDemandedBits - use DemandedElts in bitcast handling
|
2019-04-08 20:59:38 +00:00 |
|
widen_load-3.ll
|
[x86] avoid vector load narrowing with extracted store uses (PR42305)
|
2019-06-19 18:13:47 +00:00 |
|
widen_mul.ll
|
…
|
|
|
widen_shuffle-1.ll
|
[DAGCombiner][X86][SystemZ][AArch64] Combine some cases of (bitcast (build_vector constants)) between legalize types and legalize dag.
|
2019-03-04 19:12:16 +00:00 |
|
widened-broadcast.ll
|
[X86][AVX] lowerShuffleAsBroadcast - improve load folding by avoiding bitcasts
|
2019-03-13 12:20:39 +00:00 |
|
win-alloca-expander.ll
|
…
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win-catchpad-csrs.ll
|
…
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win-catchpad-nested-cxx.ll
|
…
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win-catchpad-nested.ll
|
…
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win-catchpad-varargs.ll
|
…
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win-catchpad.ll
|
…
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win-cleanuppad.ll
|
…
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win-funclet-cfi.ll
|
…
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win-mixed-ehpersonality.ll
|
…
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win-smallparams.ll
|
…
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win32-bool.ll
|
…
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win32-eh-available-externally.ll
|
…
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win32-eh-states.ll
|
…
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win32-eh.ll
|
…
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win32-pic-jumptable.ll
|
…
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win32-preemption.ll
|
…
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win32-seh-catchpad-realign.ll
|
…
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win32-seh-catchpad.ll
|
…
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win32-seh-nested-finally.ll
|
…
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win32-spill-xmm.ll
|
…
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win32-ssp.ll
|
…
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win32_sret.ll
|
…
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win64-bool.ll
|
…
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win64-byval.ll
|
…
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win64-jumptable.ll
|
…
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win64-long-double.ll
|
…
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win64-nosse-csrs.ll
|
…
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win64_alloca_dynalloca.ll
|
…
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|
win64_call_epi.ll
|
…
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|
win64_eh.ll
|
…
|
|
|
win64_eh_leaf.ll
|
[llvm-readobj] Change -long-option to --long-option in tests. NFC
|
2019-05-01 05:27:20 +00:00 |
|
win64_eh_leaf2.ll
|
…
|
|
|
win64_frame.ll
|
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
|
2019-03-13 17:07:09 +00:00 |
|
win64_nonvol.ll
|
…
|
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|
win64_params.ll
|
…
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|
win64_sibcall.ll
|
…
|
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|
win64_vararg.ll
|
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
|
2019-03-13 17:07:09 +00:00 |
|
win_chkstk.ll
|
…
|
|
|
win_coreclr_chkstk.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
win_coreclr_chkstk_liveins.mir
|
Describe stack-id as an enum
|
2019-06-17 09:13:29 +00:00 |
|
win_cst_pool.ll
|
Standardize on MSVC behavior for triples with no environment
|
2019-07-08 21:05:20 +00:00 |
|
windows-itanium-alloca.ll
|
…
|
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|
wineh-coreclr.ll
|
…
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wineh-exceptionpointer.ll
|
…
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wineh-no-ehpads.ll
|
…
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x32-cet-intrinsics.ll
|
…
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x32-function_pointer-1.ll
|
…
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x32-function_pointer-2.ll
|
…
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x32-function_pointer-3.ll
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…
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x32-indirectbr.ll
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…
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x32-landingpad.ll
|
…
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x32-lea-1.ll
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…
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x32-movtopush64.ll
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…
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x32-va_start.ll
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…
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x64-cet-intrinsics.ll
|
…
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x86-16.ll
|
…
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x86-32-intrcc.ll
|
[X86] Fix bug in x86_intrcc with arg copy elision
|
2019-02-26 02:11:25 +00:00 |
|
x86-32-vector-calling-conv.ll
|
…
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x86-64-and-mask.ll
|
…
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x86-64-arg.ll
|
…
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x86-64-asm.ll
|
…
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|
x86-64-baseptr.ll
|
[X86] Use INSERT_SUBREG rather than SUBREG_TO_REG when creating LEA64_32 during isel.
|
2019-04-04 05:00:18 +00:00 |
|
x86-64-bittest-logic.ll
|
…
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x86-64-call.ll
|
…
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x86-64-disp.ll
|
…
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x86-64-double-precision-shift-left.ll
|
…
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x86-64-double-precision-shift-right.ll
|
…
|
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|
x86-64-double-shifts-Oz-Os-O2.ll
|
…
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|
x86-64-double-shifts-var.ll
|
[X86] AMD znver2 enablement
|
2019-02-26 16:55:10 +00:00 |
|
x86-64-extend-shift.ll
|
…
|
|
|
x86-64-flags-intrinsics.ll
|
…
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x86-64-gv-offset.ll
|
…
|
|
|
x86-64-intrcc-nosse.ll
|
…
|
|
|
x86-64-intrcc.ll
|
[X86] Fix bug in x86_intrcc with arg copy elision
|
2019-02-26 02:11:25 +00:00 |
|
x86-64-jumps.ll
|
…
|
|
|
x86-64-mem.ll
|
…
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|
|
x86-64-ms_abi-vararg.ll
|
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
|
2019-03-13 17:07:09 +00:00 |
|
x86-64-pic-1.ll
|
…
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|
x86-64-pic-2.ll
|
…
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x86-64-pic-3.ll
|
…
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x86-64-pic-4.ll
|
…
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x86-64-pic-5.ll
|
…
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x86-64-pic-6.ll
|
…
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x86-64-pic-7.ll
|
…
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x86-64-pic-8.ll
|
…
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x86-64-pic-9.ll
|
…
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x86-64-pic-10.ll
|
…
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x86-64-pic-11.ll
|
…
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x86-64-pic-12.ll
|
…
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x86-64-pic.ll
|
…
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x86-64-plt-relative-reloc.ll
|
…
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x86-64-psub.ll
|
…
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x86-64-ptr-arg-simple.ll
|
…
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x86-64-ret0.ll
|
…
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x86-64-shortint.ll
|
…
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x86-64-sret-return-2.ll
|
…
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x86-64-sret-return.ll
|
…
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|
x86-64-stack-and-frame-ptr.ll
|
…
|
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x86-64-static-relo-movl.ll
|
…
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|
x86-64-tls-1.ll
|
…
|
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|
x86-64-varargs.ll
|
…
|
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|
x86-64-veccallcc.ll
|
[X86] Fix bug in vectorcall calling convention
|
2019-02-26 19:48:16 +00:00 |
|
x86-big-ret.ll
|
…
|
|
|
x86-cmov-converter.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
x86-flags-intrinsics.ll
|
…
|
|
|
x86-fold-pshufb.ll
|
…
|
|
|
x86-framelowering-trap.ll
|
…
|
|
|
x86-inline-asm-validation.ll
|
…
|
|
|
x86-interleaved-access.ll
|
[x86] split more 256-bit stores of concatenated vectors
|
2019-06-05 16:40:57 +00:00 |
|
x86-interleaved-check.ll
|
…
|
|
|
x86-interrupt_cc.ll
|
…
|
|
|
x86-interrupt_cld.ll
|
…
|
|
|
x86-interrupt_vzeroupper.ll
|
…
|
|
|
x86-mixed-alignment-dagcombine.ll
|
…
|
|
|
x86-no_caller_saved_registers-preserve.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
x86-no_caller_saved_registers.ll
|
…
|
|
|
x86-plt-relative-reloc.ll
|
…
|
|
|
x86-repmov-copy-eflags.ll
|
…
|
|
|
x86-sanitizer-shrink-wrapping.ll
|
…
|
|
|
x86-setcc-int-to-fp-combine.ll
|
…
|
|
|
x86-shifts.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
x86-shrink-wrap-unwind.ll
|
…
|
|
|
x86-shrink-wrapping.ll
|
[Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr)
|
2019-06-25 17:29:18 +00:00 |
|
x86-store-gv-addr.ll
|
…
|
|
|
x86-upgrade-avx-vbroadcast.ll
|
…
|
|
|
x86-upgrade-avx2-vbroadcast.ll
|
…
|
|
|
x86-win64-shrink-wrapping.ll
|
…
|
|
|
x86_64-mul-by-const.ll
|
…
|
|
|
x87.ll
|
…
|
|
|
xaluo.ll
|
[DAGCombiner][X86][SystemZ] Canonicalize SSUBO with immediate RHS to SADDO by negating the immediate.
|
2019-04-09 18:33:56 +00:00 |
|
xchg-nofold.ll
|
[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
|
2019-06-13 13:56:19 +00:00 |
|
xmm-r64.ll
|
…
|
|
|
xmulo.ll
|
…
|
|
|
xop-ifma.ll
|
Revert r363802, r363850, and r363856 "[TargetLowering] SimplifyDemandedBits..."
|
2019-06-25 01:32:42 +00:00 |
|
xop-intrinsics-fast-isel.ll
|
…
|
|
|
xop-intrinsics-x86_64-upgrade.ll
|
…
|
|
|
xop-intrinsics-x86_64.ll
|
…
|
|
|
xop-mask-comments.ll
|
…
|
|
|
xop-pcmov.ll
|
…
|
|
|
xor-combine-debugloc.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
xor-icmp.ll
|
…
|
|
|
xor-select-i1-combine.ll
|
…
|
|
|
xor.ll
|
[DAGCombine][X86][AArch64][AMDGPU] (x - y) + -1 -> add (xor y, -1), x fold. Try 3
|
2019-05-30 20:37:29 +00:00 |
|
xray-attribute-instrumentation.ll
|
…
|
|
|
xray-custom-log.ll
|
…
|
|
|
xray-empty-firstmbb.mir
|
…
|
|
|
xray-empty-function.mir
|
…
|
|
|
xray-log-args.ll
|
…
|
|
|
xray-loop-detection.ll
|
…
|
|
|
xray-multiplerets-in-blocks.mir
|
…
|
|
|
xray-section-group.ll
|
…
|
|
|
xray-selective-instrumentation-miss.ll
|
…
|
|
|
xray-selective-instrumentation.ll
|
…
|
|
|
xray-tail-call-sled.ll
|
…
|
|
|
xray-typed-event-log.ll
|
…
|
|
|
xtest.ll
|
…
|
|
|
zero-remat.ll
|
…
|
|
|
zext-demanded.ll
|
Revert r356996 "[DAG] Avoid smart constructor-based dangling nodes."
|
2019-03-27 19:54:41 +00:00 |
|
zext-extract_subreg.ll
|
…
|
|
|
zext-fold.ll
|
…
|
|
|
zext-inreg-0.ll
|
…
|
|
|
zext-inreg-1.ll
|
…
|
|
|
zext-logicop-shift-load.ll
|
[TargetLowering][X86] Teach SimplifyDemandedBits to use ShrinkDemandedOp on ISD::SHL nodes.
|
2019-04-12 06:49:28 +00:00 |
|
zext-sext.ll
|
[DAGCombiner][X86][AArch64][AMDGPU] (x + C) - y -> (x - y) + C fold. Try 3
|
2019-05-30 20:36:54 +00:00 |
|
zext-shl.ll
|
…
|
|
|
zext-trunc.ll
|
…
|
|
|
zlib-longest-match.ll
|
…
|
|
