llvm-project/llvm/lib/Target/SystemZ
Rafael Espindola b91455b5c0 Refactor a lot of duplicated code for stub output.
This also moves it earlier so that it they are produced before we print
an end symbol for the data section.

llvm-svn: 234315
2015-04-07 13:42:44 +00:00
..
AsmParser [SystemZ] Support all TLS access models - MC part 2015-02-18 09:11:36 +00:00
Disassembler Pass an ArrayRef to MCDisassembler::getInstruction. 2014-11-12 02:04:27 +00:00
InstPrinter [MCInstPrinter] Enable MCInstPrinter to change its behavior based on the 2015-03-27 20:36:02 +00:00
MCTargetDesc Replace the MCSubtargetInfo parameter with a Triple when creating 2015-03-31 00:10:04 +00:00
TargetInfo Prune redundant dependencies in LLVMBuild.txt. 2013-12-11 00:30:57 +00:00
CMakeLists.txt [SystemZ] Provide basic TargetTransformInfo implementation 2015-03-31 12:52:27 +00:00
LLVMBuild.txt [SystemZ] Add Analysis to required_libraries (fall-out from r233688) 2015-03-31 15:16:13 +00:00
Makefile Reinstate "Nuke the old JIT." 2014-09-02 22:28:02 +00:00
README.txt Add TargetLowering::prepareVolatileOrAtomicLoad 2013-12-10 10:49:34 +00:00
SystemZ.h [SystemZ] Support transactional execution on zEC12 2015-04-01 12:51:43 +00:00
SystemZ.td
SystemZAsmPrinter.cpp Refactor a lot of duplicated code for stub output. 2015-04-07 13:42:44 +00:00
SystemZAsmPrinter.h Refactor a lot of duplicated code for stub output. 2015-04-07 13:42:44 +00:00
SystemZCallingConv.cpp
SystemZCallingConv.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SystemZCallingConv.td [SystemZ] Use SystemZCallingConv.td to define callee-saved registers 2014-07-10 11:44:37 +00:00
SystemZConstantPoolValue.cpp [SystemZ] Support all TLS access models - CodeGen part 2015-02-18 09:13:27 +00:00
SystemZConstantPoolValue.h [SystemZ] Support all TLS access models - CodeGen part 2015-02-18 09:13:27 +00:00
SystemZElimCompare.cpp Removing LLVM_EXPLICIT, as MSVC 2012 was the last reason for requiring the macro. NFC; LLVM edition. 2015-02-15 22:00:20 +00:00
SystemZFrameLowering.cpp Fix undefined behavior (left shift of negative value) in SystemZ backend. 2014-08-20 21:56:43 +00:00
SystemZFrameLowering.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SystemZISelDAGToDAG.cpp [SystemZ] Support RISBGN instruction on zEC12 2015-03-31 12:58:17 +00:00
SystemZISelLowering.cpp [SystemZ] Support transactional execution on zEC12 2015-04-01 12:51:43 +00:00
SystemZISelLowering.h [SystemZ] Support transactional execution on zEC12 2015-04-01 12:51:43 +00:00
SystemZInstrBuilder.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SystemZInstrFP.td Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. 2014-11-26 00:46:26 +00:00
SystemZInstrFormats.td [SystemZ] Support transactional execution on zEC12 2015-04-01 12:51:43 +00:00
SystemZInstrInfo.cpp [SystemZ] Support RISBGN instruction on zEC12 2015-03-31 12:58:17 +00:00
SystemZInstrInfo.h ArrayRefize memory operand folding. NFC. 2015-02-28 12:04:00 +00:00
SystemZInstrInfo.td [SystemZ] Support transactional execution on zEC12 2015-04-01 12:51:43 +00:00
SystemZLDCleanup.cpp [SystemZ] Support all TLS access models - CodeGen part 2015-02-18 09:13:27 +00:00
SystemZLongBranch.cpp Have MachineFunction cache a pointer to the subtarget to make lookups 2014-08-05 02:39:49 +00:00
SystemZMCInstLower.cpp [SystemZ] Support all TLS access models - CodeGen part 2015-02-18 09:13:27 +00:00
SystemZMCInstLower.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SystemZMachineFunctionInfo.cpp
SystemZMachineFunctionInfo.h [SystemZ] Support all TLS access models - CodeGen part 2015-02-18 09:13:27 +00:00
SystemZOperands.td [SystemZ] Support all TLS access models - MC part 2015-02-18 09:11:36 +00:00
SystemZOperators.td [SystemZ] Support transactional execution on zEC12 2015-04-01 12:51:43 +00:00
SystemZPatterns.td [SystemZ] Avoid using i8 constants for immediate fields 2014-07-10 10:52:51 +00:00
SystemZProcessors.td [SystemZ] Support transactional execution on zEC12 2015-04-01 12:51:43 +00:00
SystemZRegisterInfo.cpp Have getCallPreservedMask and getThisCallPreservedMask take a 2015-03-11 22:42:13 +00:00
SystemZRegisterInfo.h Have getCallPreservedMask and getThisCallPreservedMask take a 2015-03-11 22:42:13 +00:00
SystemZRegisterInfo.td [SystemZ] Fix FPR dwarf numbering 2014-07-10 10:45:11 +00:00
SystemZSelectionDAGInfo.cpp Demote vectors to arrays. No functionality change. 2015-02-19 15:26:17 +00:00
SystemZSelectionDAGInfo.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SystemZShortenInst.cpp Have MachineFunction cache a pointer to the subtarget to make lookups 2014-08-05 02:39:49 +00:00
SystemZSubtarget.cpp [SystemZ] Support transactional execution on zEC12 2015-04-01 12:51:43 +00:00
SystemZSubtarget.h [SystemZ] Support transactional execution on zEC12 2015-04-01 12:51:43 +00:00
SystemZTargetMachine.cpp [SystemZ] Provide basic TargetTransformInfo implementation 2015-03-31 12:52:27 +00:00
SystemZTargetMachine.h [SystemZ] Provide basic TargetTransformInfo implementation 2015-03-31 12:52:27 +00:00
SystemZTargetTransformInfo.cpp [SystemZ] Use POPCNT instruction on z196 2015-03-31 12:56:33 +00:00
SystemZTargetTransformInfo.h [SystemZ] Use POPCNT instruction on z196 2015-03-31 12:56:33 +00:00

README.txt

//===---------------------------------------------------------------------===//
// Random notes about and ideas for the SystemZ backend.
//===---------------------------------------------------------------------===//

The initial backend is deliberately restricted to z10.  We should add support
for later architectures at some point.

--

SystemZDAGToDAGISel::SelectInlineAsmMemoryOperand() is passed "m" for all
inline asm memory constraints; it doesn't get to see the original constraint.
This means that it must conservatively treat all inline asm constraints
as the most restricted type, "R".

--

If an inline asm ties an i32 "r" result to an i64 input, the input
will be treated as an i32, leaving the upper bits uninitialised.
For example:

define void @f4(i32 *%dst) {
  %val = call i32 asm "blah $0", "=r,0" (i64 103)
  store i32 %val, i32 *%dst
  ret void
}

from CodeGen/SystemZ/asm-09.ll will use LHI rather than LGHI.
to load 103.  This seems to be a general target-independent problem.

--

The tuning of the choice between LOAD ADDRESS (LA) and addition in
SystemZISelDAGToDAG.cpp is suspect.  It should be tweaked based on
performance measurements.

--

There is no scheduling support.

--

We don't use the BRANCH ON INDEX instructions.

--

We might want to use BRANCH ON CONDITION for conditional indirect calls
and conditional returns.

--

We don't use the TEST DATA CLASS instructions.

--

We could use the generic floating-point forms of LOAD COMPLEMENT,
LOAD NEGATIVE and LOAD POSITIVE in cases where we don't need the
condition codes.  For example, we could use LCDFR instead of LCDBR.

--

We only use MVC, XC and CLC for constant-length block operations.
We could extend them to variable-length operations too,
using EXECUTE RELATIVE LONG.

MVCIN, MVCLE and CLCLE may be worthwhile too.

--

We don't use CUSE or the TRANSLATE family of instructions for string
operations.  The TRANSLATE ones are probably more difficult to exploit.

--

We don't take full advantage of builtins like fabsl because the calling
conventions require f128s to be returned by invisible reference.

--

ADD LOGICAL WITH SIGNED IMMEDIATE could be useful when we need to
produce a carry.  SUBTRACT LOGICAL IMMEDIATE could be useful when we
need to produce a borrow.  (Note that there are no memory forms of
ADD LOGICAL WITH CARRY and SUBTRACT LOGICAL WITH BORROW, so the high
part of 128-bit memory operations would probably need to be done
via a register.)

--

We don't use the halfword forms of LOAD REVERSED and STORE REVERSED
(LRVH and STRVH).

--

We don't use ICM or STCM.

--

DAGCombiner doesn't yet fold truncations of extended loads.  Functions like:

    unsigned long f (unsigned long x, unsigned short *y)
    {
      return (x << 32) | *y;
    }

therefore end up as:

        sllg    %r2, %r2, 32
        llgh    %r0, 0(%r3)
        lr      %r2, %r0
        br      %r14

but truncating the load would give:

        sllg    %r2, %r2, 32
        lh      %r2, 0(%r3)
        br      %r14

--

Functions like:

define i64 @f1(i64 %a) {
  %and = and i64 %a, 1
  ret i64 %and
}

ought to be implemented as:

        lhi     %r0, 1
        ngr     %r2, %r0
        br      %r14

but two-address optimisations reverse the order of the AND and force:

        lhi     %r0, 1
        ngr     %r0, %r2
        lgr     %r2, %r0
        br      %r14

CodeGen/SystemZ/and-04.ll has several examples of this.

--

Out-of-range displacements are usually handled by loading the full
address into a register.  In many cases it would be better to create
an anchor point instead.  E.g. for:

define void @f4a(i128 *%aptr, i64 %base) {
  %addr = add i64 %base, 524288
  %bptr = inttoptr i64 %addr to i128 *
  %a = load volatile i128 *%aptr
  %b = load i128 *%bptr
  %add = add i128 %a, %b
  store i128 %add, i128 *%aptr
  ret void
}

(from CodeGen/SystemZ/int-add-08.ll) we load %base+524288 and %base+524296
into separate registers, rather than using %base+524288 as a base for both.

--

Dynamic stack allocations round the size to 8 bytes and then allocate
that rounded amount.  It would be simpler to subtract the unrounded
size from the copy of the stack pointer and then align the result.
See CodeGen/SystemZ/alloca-01.ll for an example.

--

If needed, we can support 16-byte atomics using LPQ, STPQ and CSDG.

--

We might want to model all access registers and use them to spill
32-bit values.