llvm-project/llvm/test/CodeGen
Nico Weber 71d64f72f9 Revert "[MIR] Target specific MIR formating and parsing"
This reverts commit 3ef05d85be.
It broke check-llvm on many bots, see comments on D69836.
2020-01-08 22:50:49 -05:00
..
AArch64 Revert "Merge memtag instructions with adjacent stack slots." 2020-01-08 14:36:12 -08:00
AMDGPU Revert "[MIR] Target specific MIR formating and parsing" 2020-01-08 22:50:49 -05:00
ARC
ARM [ARM][MVE] Enable masked gathers from vector of pointers 2020-01-08 13:43:12 +00:00
AVR
BPF
Generic
Hexagon [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal' 2020-01-03 03:26:41 +00:00
Inputs
Lanai
MIR llc: Change behavior of -mcpu with existing attribute 2020-01-07 10:10:25 -05:00
MSP430
Mips GlobalISel: Correct result type for G_FCMP in lowerFPTOUI 2020-01-06 17:21:51 -05:00
NVPTX
PowerPC [PowerPC] when folding rlwinm+rlwinm. to andi., we should use first rlwinm 2020-01-08 20:59:08 -05:00
RISCV Move tail call disabling code to target independent code 2020-01-03 11:27:41 -08:00
SPARC
SystemZ [SystemZ] Extend fp-strict-alias test case 2020-01-07 12:44:51 +01:00
Thumb
Thumb2 [ARM,MVE] Intrinsics for variable shift instructions. 2020-01-08 14:42:24 +00:00
WebAssembly [WebAssembly] Fix landingpad-only case in Emscripten EH 2020-01-06 17:02:32 -08:00
WinCFGuard
WinEH
X86 [X86] Remove EFLAGS from live-in lists in X86FlagsCopyLowering. 2020-01-08 16:36:03 -08:00
XCore