forked from OSchip/llvm-project
32 lines
875 B
LLVM
32 lines
875 B
LLVM
; RUN: llc < %s -march=xcore > %t1.s
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; RUN: grep "bl __misaligned_load" %t1.s | count 1
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; RUN: grep ld16s %t1.s | count 2
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; RUN: grep ldw %t1.s | count 2
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; RUN: grep shl %t1.s | count 2
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; RUN: grep shr %t1.s | count 1
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; RUN: grep zext %t1.s | count 1
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; RUN: grep "or " %t1.s | count 2
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; Byte aligned load. Expands to call to __misaligned_load.
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define i32 @align1(i32* %p) nounwind {
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entry:
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%0 = load i32* %p, align 1 ; <i32> [#uses=1]
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ret i32 %0
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}
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; Half word aligned load. Expands to two 16bit loads.
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define i32 @align2(i32* %p) nounwind {
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entry:
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%0 = load i32* %p, align 2 ; <i32> [#uses=1]
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ret i32 %0
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}
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@a = global [5 x i8] zeroinitializer, align 4
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; Constant offset from word aligned base. Expands to two 32bit loads.
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define i32 @align3() nounwind {
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entry:
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%0 = load i32* bitcast (i8* getelementptr ([5 x i8]* @a, i32 0, i32 1) to i32*), align 1
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ret i32 %0
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}
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