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Thomas Lively 5e09e9979b [WebAssembly] Prototype extending pairwise add instructions 
As proposed in https://github.com/WebAssembly/simd/pull/380. This commit makes
the new instructions available only via clang builtins and LLVM intrinsics to
make their use opt-in while they are still being evaluated for inclusion in the
SIMD proposal.

Depends on D93771.

Differential Revision: https://reviews.llvm.org/D93775
 		2020-12-28 14:11:14 -08:00
..
AArch64 [AArch64] Updating .arch_extension negative tests 2020-12-18 15:57:11 +00:00
AMDGPU [AMDGPU][MC][NFC] Added more tests for flat_global 2020-12-28 23:00:56 +03:00
ARM [llvm-readobj] - For SHT_REL relocations, don't display an addend. 2020-12-14 12:03:00 +03:00
AVR [AVRInstPrinter] printOperand: support llvm-objdump --print-imm-hex 2020-07-12 08:14:52 -07:00
AsmParser [AsmParser] make .ascii support spaces as separators 2020-12-20 22:41:00 -08:00
BPF [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
COFF [CodeView] Fix inline sites that are missing code offsets. 2020-12-07 13:01:53 -08:00
Disassembler [WebAssembly][SIMD] Rename shuffle, swizzle, and load_splats 2020-12-22 14:29:06 -08:00
ELF [MC][test] Reorganize .cfi_* tests 2020-12-21 17:18:28 -08:00
Hexagon [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
Lanai
…
MSP430 [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
MachO [Triple][MachO] Define "arm64e", an AArch64 subarch for Pointer Auth. 2020-12-03 07:53:59 -08:00
Mips [MC][ELF] Allow STT_SECTION referencing SHF_MERGE on REL targets 2020-12-20 18:37:14 -08:00
PowerPC [PowerPC] Parse and ignore .machine 2020-12-28 12:20:40 -08:00
RISCV [RISCV] Improve VMConstraint checking on more unary and nullary instructions. 2020-12-26 18:47:59 -08:00
Sparc [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
SystemZ [SystemZ] Adding extra extended mnemonics for SystemZ target 2020-12-02 08:25:31 -05:00
VE [VE] Add missing BCR format 2020-10-29 23:30:49 +09:00
WebAssembly [WebAssembly] Prototype extending pairwise add instructions 2020-12-28 14:11:14 -08:00
X86 [MC][test] Reorganize .cfi_* tests 2020-12-21 17:18:28 -08:00