forked from OSchip/llvm-project
1010 lines
32 KiB
LLVM
1010 lines
32 KiB
LLVM
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
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; RUN: --riscv-no-aliases < %s | FileCheck %s
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declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
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<vscale x 1 x half>,
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<vscale x 1 x half>,
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i64);
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define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f16_nxv1f16
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
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; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
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<vscale x 1 x half> %0,
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<vscale x 1 x half> %1,
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i64 %2)
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ret <vscale x 1 x i1> %a
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}
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declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16(
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<vscale x 1 x i1>,
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<vscale x 1 x half>,
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<vscale x 1 x half>,
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<vscale x 1 x i1>,
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i64);
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define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu
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; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
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%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
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<vscale x 1 x half> %1,
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<vscale x 1 x half> %2,
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i64 %4)
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%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16(
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<vscale x 1 x i1> %0,
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<vscale x 1 x half> %2,
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<vscale x 1 x half> %3,
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<vscale x 1 x i1> %mask,
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i64 %4)
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ret <vscale x 1 x i1> %a
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}
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declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
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<vscale x 2 x half>,
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<vscale x 2 x half>,
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i64);
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define <vscale x 2 x i1> @intrinsic_vmfeq_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f16_nxv2f16
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
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; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
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<vscale x 2 x half> %0,
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<vscale x 2 x half> %1,
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i64 %2)
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ret <vscale x 2 x i1> %a
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}
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declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16(
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<vscale x 2 x i1>,
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<vscale x 2 x half>,
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<vscale x 2 x half>,
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<vscale x 2 x i1>,
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i64);
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define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu
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; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
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%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
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<vscale x 2 x half> %1,
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<vscale x 2 x half> %2,
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i64 %4)
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%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16(
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<vscale x 2 x i1> %0,
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<vscale x 2 x half> %2,
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<vscale x 2 x half> %3,
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<vscale x 2 x i1> %mask,
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i64 %4)
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ret <vscale x 2 x i1> %a
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}
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declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
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<vscale x 4 x half>,
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<vscale x 4 x half>,
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i64);
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define <vscale x 4 x i1> @intrinsic_vmfeq_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f16_nxv4f16
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
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; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
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<vscale x 4 x half> %0,
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<vscale x 4 x half> %1,
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i64 %2)
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ret <vscale x 4 x i1> %a
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}
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declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16(
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<vscale x 4 x i1>,
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<vscale x 4 x half>,
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<vscale x 4 x half>,
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<vscale x 4 x i1>,
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i64);
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define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu
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; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
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%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
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<vscale x 4 x half> %1,
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<vscale x 4 x half> %2,
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i64 %4)
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%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16(
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<vscale x 4 x i1> %0,
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<vscale x 4 x half> %2,
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<vscale x 4 x half> %3,
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<vscale x 4 x i1> %mask,
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i64 %4)
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ret <vscale x 4 x i1> %a
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}
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declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
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<vscale x 8 x half>,
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<vscale x 8 x half>,
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i64);
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define <vscale x 8 x i1> @intrinsic_vmfeq_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmfeq_vv_nxv8f16_nxv8f16
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
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; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
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<vscale x 8 x half> %0,
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<vscale x 8 x half> %1,
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i64 %2)
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ret <vscale x 8 x i1> %a
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}
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declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16(
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<vscale x 8 x i1>,
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<vscale x 8 x half>,
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<vscale x 8 x half>,
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<vscale x 8 x i1>,
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i64);
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define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu
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; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
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%mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
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<vscale x 8 x half> %1,
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<vscale x 8 x half> %2,
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i64 %4)
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%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16(
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<vscale x 8 x i1> %0,
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<vscale x 8 x half> %2,
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<vscale x 8 x half> %3,
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<vscale x 8 x i1> %mask,
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i64 %4)
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ret <vscale x 8 x i1> %a
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}
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declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
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<vscale x 16 x half>,
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<vscale x 16 x half>,
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i64);
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define <vscale x 16 x i1> @intrinsic_vmfeq_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmfeq_vv_nxv16f16_nxv16f16
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
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; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
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<vscale x 16 x half> %0,
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<vscale x 16 x half> %1,
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i64 %2)
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ret <vscale x 16 x i1> %a
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}
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declare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16(
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<vscale x 16 x i1>,
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<vscale x 16 x half>,
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<vscale x 16 x half>,
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<vscale x 16 x i1>,
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i64);
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define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu
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; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
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%mask = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
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<vscale x 16 x half> %1,
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<vscale x 16 x half> %2,
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i64 %4)
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%a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16(
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<vscale x 16 x i1> %0,
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<vscale x 16 x half> %2,
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<vscale x 16 x half> %3,
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<vscale x 16 x i1> %mask,
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i64 %4)
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ret <vscale x 16 x i1> %a
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}
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declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
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<vscale x 1 x float>,
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<vscale x 1 x float>,
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i64);
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define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f32_nxv1f32
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
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; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
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<vscale x 1 x float> %0,
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<vscale x 1 x float> %1,
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i64 %2)
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ret <vscale x 1 x i1> %a
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}
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declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32(
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<vscale x 1 x i1>,
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<vscale x 1 x float>,
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<vscale x 1 x float>,
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<vscale x 1 x i1>,
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i64);
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define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu
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; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
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%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
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<vscale x 1 x float> %1,
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<vscale x 1 x float> %2,
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i64 %4)
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%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32(
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<vscale x 1 x i1> %0,
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<vscale x 1 x float> %2,
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<vscale x 1 x float> %3,
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<vscale x 1 x i1> %mask,
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i64 %4)
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ret <vscale x 1 x i1> %a
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}
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declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
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<vscale x 2 x float>,
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<vscale x 2 x float>,
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i64);
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define <vscale x 2 x i1> @intrinsic_vmfeq_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f32_nxv2f32
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
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; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
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<vscale x 2 x float> %0,
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<vscale x 2 x float> %1,
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i64 %2)
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ret <vscale x 2 x i1> %a
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}
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declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32(
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<vscale x 2 x i1>,
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<vscale x 2 x float>,
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<vscale x 2 x float>,
|
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<vscale x 2 x i1>,
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i64);
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define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu
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; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
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%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
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<vscale x 2 x float> %1,
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<vscale x 2 x float> %2,
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i64 %4)
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%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32(
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<vscale x 2 x i1> %0,
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<vscale x 2 x float> %2,
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<vscale x 2 x float> %3,
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<vscale x 2 x i1> %mask,
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i64 %4)
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ret <vscale x 2 x i1> %a
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}
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declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
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<vscale x 4 x float>,
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<vscale x 4 x float>,
|
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i64);
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define <vscale x 4 x i1> @intrinsic_vmfeq_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f32_nxv4f32
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
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; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
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<vscale x 4 x float> %0,
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<vscale x 4 x float> %1,
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i64 %2)
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ret <vscale x 4 x i1> %a
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}
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declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32(
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<vscale x 4 x i1>,
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<vscale x 4 x float>,
|
|
<vscale x 4 x float>,
|
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<vscale x 4 x i1>,
|
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i64);
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define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu
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; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
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%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
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<vscale x 4 x float> %1,
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<vscale x 4 x float> %2,
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i64 %4)
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%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32(
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<vscale x 4 x i1> %0,
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<vscale x 4 x float> %2,
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<vscale x 4 x float> %3,
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<vscale x 4 x i1> %mask,
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i64 %4)
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ret <vscale x 4 x i1> %a
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}
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declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
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<vscale x 8 x float>,
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|
<vscale x 8 x float>,
|
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i64);
|
|
|
|
define <vscale x 8 x i1> @intrinsic_vmfeq_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_vv_nxv8f32_nxv8f32
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
|
|
; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
|
|
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
|
|
<vscale x 8 x float> %0,
|
|
<vscale x 8 x float> %1,
|
|
i64 %2)
|
|
|
|
ret <vscale x 8 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32(
|
|
<vscale x 8 x i1>,
|
|
<vscale x 8 x float>,
|
|
<vscale x 8 x float>,
|
|
<vscale x 8 x i1>,
|
|
i64);
|
|
|
|
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu
|
|
; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
|
|
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
|
|
<vscale x 8 x float> %1,
|
|
<vscale x 8 x float> %2,
|
|
i64 %4)
|
|
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32(
|
|
<vscale x 8 x i1> %0,
|
|
<vscale x 8 x float> %2,
|
|
<vscale x 8 x float> %3,
|
|
<vscale x 8 x i1> %mask,
|
|
i64 %4)
|
|
|
|
ret <vscale x 8 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64(
|
|
<vscale x 1 x double>,
|
|
<vscale x 1 x double>,
|
|
i64);
|
|
|
|
define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f64_nxv1f64
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
|
|
; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
|
|
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64(
|
|
<vscale x 1 x double> %0,
|
|
<vscale x 1 x double> %1,
|
|
i64 %2)
|
|
|
|
ret <vscale x 1 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64(
|
|
<vscale x 1 x i1>,
|
|
<vscale x 1 x double>,
|
|
<vscale x 1 x double>,
|
|
<vscale x 1 x i1>,
|
|
i64);
|
|
|
|
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu
|
|
; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
|
|
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64(
|
|
<vscale x 1 x double> %1,
|
|
<vscale x 1 x double> %2,
|
|
i64 %4)
|
|
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64(
|
|
<vscale x 1 x i1> %0,
|
|
<vscale x 1 x double> %2,
|
|
<vscale x 1 x double> %3,
|
|
<vscale x 1 x i1> %mask,
|
|
i64 %4)
|
|
|
|
ret <vscale x 1 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64(
|
|
<vscale x 2 x double>,
|
|
<vscale x 2 x double>,
|
|
i64);
|
|
|
|
define <vscale x 2 x i1> @intrinsic_vmfeq_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f64_nxv2f64
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
|
|
; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
|
|
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64(
|
|
<vscale x 2 x double> %0,
|
|
<vscale x 2 x double> %1,
|
|
i64 %2)
|
|
|
|
ret <vscale x 2 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64(
|
|
<vscale x 2 x i1>,
|
|
<vscale x 2 x double>,
|
|
<vscale x 2 x double>,
|
|
<vscale x 2 x i1>,
|
|
i64);
|
|
|
|
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu
|
|
; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
|
|
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64(
|
|
<vscale x 2 x double> %1,
|
|
<vscale x 2 x double> %2,
|
|
i64 %4)
|
|
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64(
|
|
<vscale x 2 x i1> %0,
|
|
<vscale x 2 x double> %2,
|
|
<vscale x 2 x double> %3,
|
|
<vscale x 2 x i1> %mask,
|
|
i64 %4)
|
|
|
|
ret <vscale x 2 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64(
|
|
<vscale x 4 x double>,
|
|
<vscale x 4 x double>,
|
|
i64);
|
|
|
|
define <vscale x 4 x i1> @intrinsic_vmfeq_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f64_nxv4f64
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
|
|
; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
|
|
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64(
|
|
<vscale x 4 x double> %0,
|
|
<vscale x 4 x double> %1,
|
|
i64 %2)
|
|
|
|
ret <vscale x 4 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64(
|
|
<vscale x 4 x i1>,
|
|
<vscale x 4 x double>,
|
|
<vscale x 4 x double>,
|
|
<vscale x 4 x i1>,
|
|
i64);
|
|
|
|
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu
|
|
; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
|
|
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64(
|
|
<vscale x 4 x double> %1,
|
|
<vscale x 4 x double> %2,
|
|
i64 %4)
|
|
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64(
|
|
<vscale x 4 x i1> %0,
|
|
<vscale x 4 x double> %2,
|
|
<vscale x 4 x double> %3,
|
|
<vscale x 4 x i1> %mask,
|
|
i64 %4)
|
|
|
|
ret <vscale x 4 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16(
|
|
<vscale x 1 x half>,
|
|
half,
|
|
i64);
|
|
|
|
define <vscale x 1 x i1> @intrinsic_vmfeq_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f16_f16
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
|
|
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16(
|
|
<vscale x 1 x half> %0,
|
|
half %1,
|
|
i64 %2)
|
|
|
|
ret <vscale x 1 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
|
|
<vscale x 1 x i1>,
|
|
<vscale x 1 x half>,
|
|
half,
|
|
<vscale x 1 x i1>,
|
|
i64);
|
|
|
|
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
|
|
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
|
|
<vscale x 1 x i1> %0,
|
|
<vscale x 1 x half> %1,
|
|
half %2,
|
|
<vscale x 1 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret <vscale x 1 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16(
|
|
<vscale x 2 x half>,
|
|
half,
|
|
i64);
|
|
|
|
define <vscale x 2 x i1> @intrinsic_vmfeq_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f16_f16
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
|
|
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16(
|
|
<vscale x 2 x half> %0,
|
|
half %1,
|
|
i64 %2)
|
|
|
|
ret <vscale x 2 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
|
|
<vscale x 2 x i1>,
|
|
<vscale x 2 x half>,
|
|
half,
|
|
<vscale x 2 x i1>,
|
|
i64);
|
|
|
|
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
|
|
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
|
|
<vscale x 2 x i1> %0,
|
|
<vscale x 2 x half> %1,
|
|
half %2,
|
|
<vscale x 2 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret <vscale x 2 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16(
|
|
<vscale x 4 x half>,
|
|
half,
|
|
i64);
|
|
|
|
define <vscale x 4 x i1> @intrinsic_vmfeq_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f16_f16
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
|
|
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16(
|
|
<vscale x 4 x half> %0,
|
|
half %1,
|
|
i64 %2)
|
|
|
|
ret <vscale x 4 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
|
|
<vscale x 4 x i1>,
|
|
<vscale x 4 x half>,
|
|
half,
|
|
<vscale x 4 x i1>,
|
|
i64);
|
|
|
|
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
|
|
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
|
|
<vscale x 4 x i1> %0,
|
|
<vscale x 4 x half> %1,
|
|
half %2,
|
|
<vscale x 4 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret <vscale x 4 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16(
|
|
<vscale x 8 x half>,
|
|
half,
|
|
i64);
|
|
|
|
define <vscale x 8 x i1> @intrinsic_vmfeq_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv8f16_f16
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
|
|
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16(
|
|
<vscale x 8 x half> %0,
|
|
half %1,
|
|
i64 %2)
|
|
|
|
ret <vscale x 8 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
|
|
<vscale x 8 x i1>,
|
|
<vscale x 8 x half>,
|
|
half,
|
|
<vscale x 8 x i1>,
|
|
i64);
|
|
|
|
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
|
|
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
|
|
<vscale x 8 x i1> %0,
|
|
<vscale x 8 x half> %1,
|
|
half %2,
|
|
<vscale x 8 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret <vscale x 8 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16(
|
|
<vscale x 16 x half>,
|
|
half,
|
|
i64);
|
|
|
|
define <vscale x 16 x i1> @intrinsic_vmfeq_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv16f16_f16
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
|
|
%a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16(
|
|
<vscale x 16 x half> %0,
|
|
half %1,
|
|
i64 %2)
|
|
|
|
ret <vscale x 16 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
|
|
<vscale x 16 x i1>,
|
|
<vscale x 16 x half>,
|
|
half,
|
|
<vscale x 16 x i1>,
|
|
i64);
|
|
|
|
define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
|
|
%a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
|
|
<vscale x 16 x i1> %0,
|
|
<vscale x 16 x half> %1,
|
|
half %2,
|
|
<vscale x 16 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret <vscale x 16 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32.f32(
|
|
<vscale x 1 x float>,
|
|
float,
|
|
i64);
|
|
|
|
define <vscale x 1 x i1> @intrinsic_vmfeq_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f32_f32
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
|
|
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32.f32(
|
|
<vscale x 1 x float> %0,
|
|
float %1,
|
|
i64 %2)
|
|
|
|
ret <vscale x 1 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
|
|
<vscale x 1 x i1>,
|
|
<vscale x 1 x float>,
|
|
float,
|
|
<vscale x 1 x i1>,
|
|
i64);
|
|
|
|
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
|
|
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
|
|
<vscale x 1 x i1> %0,
|
|
<vscale x 1 x float> %1,
|
|
float %2,
|
|
<vscale x 1 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret <vscale x 1 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32.f32(
|
|
<vscale x 2 x float>,
|
|
float,
|
|
i64);
|
|
|
|
define <vscale x 2 x i1> @intrinsic_vmfeq_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f32_f32
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
|
|
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32.f32(
|
|
<vscale x 2 x float> %0,
|
|
float %1,
|
|
i64 %2)
|
|
|
|
ret <vscale x 2 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
|
|
<vscale x 2 x i1>,
|
|
<vscale x 2 x float>,
|
|
float,
|
|
<vscale x 2 x i1>,
|
|
i64);
|
|
|
|
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
|
|
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
|
|
<vscale x 2 x i1> %0,
|
|
<vscale x 2 x float> %1,
|
|
float %2,
|
|
<vscale x 2 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret <vscale x 2 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32.f32(
|
|
<vscale x 4 x float>,
|
|
float,
|
|
i64);
|
|
|
|
define <vscale x 4 x i1> @intrinsic_vmfeq_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f32_f32
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
|
|
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32.f32(
|
|
<vscale x 4 x float> %0,
|
|
float %1,
|
|
i64 %2)
|
|
|
|
ret <vscale x 4 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
|
|
<vscale x 4 x i1>,
|
|
<vscale x 4 x float>,
|
|
float,
|
|
<vscale x 4 x i1>,
|
|
i64);
|
|
|
|
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
|
|
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
|
|
<vscale x 4 x i1> %0,
|
|
<vscale x 4 x float> %1,
|
|
float %2,
|
|
<vscale x 4 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret <vscale x 4 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32.f32(
|
|
<vscale x 8 x float>,
|
|
float,
|
|
i64);
|
|
|
|
define <vscale x 8 x i1> @intrinsic_vmfeq_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv8f32_f32
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
|
|
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32.f32(
|
|
<vscale x 8 x float> %0,
|
|
float %1,
|
|
i64 %2)
|
|
|
|
ret <vscale x 8 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
|
|
<vscale x 8 x i1>,
|
|
<vscale x 8 x float>,
|
|
float,
|
|
<vscale x 8 x i1>,
|
|
i64);
|
|
|
|
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
|
|
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
|
|
<vscale x 8 x i1> %0,
|
|
<vscale x 8 x float> %1,
|
|
float %2,
|
|
<vscale x 8 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret <vscale x 8 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64.f64(
|
|
<vscale x 1 x double>,
|
|
double,
|
|
i64);
|
|
|
|
define <vscale x 1 x i1> @intrinsic_vmfeq_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f64_f64
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
|
|
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64.f64(
|
|
<vscale x 1 x double> %0,
|
|
double %1,
|
|
i64 %2)
|
|
|
|
ret <vscale x 1 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64.f64(
|
|
<vscale x 1 x i1>,
|
|
<vscale x 1 x double>,
|
|
double,
|
|
<vscale x 1 x i1>,
|
|
i64);
|
|
|
|
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f64_f64
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
|
|
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64.f64(
|
|
<vscale x 1 x i1> %0,
|
|
<vscale x 1 x double> %1,
|
|
double %2,
|
|
<vscale x 1 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret <vscale x 1 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64.f64(
|
|
<vscale x 2 x double>,
|
|
double,
|
|
i64);
|
|
|
|
define <vscale x 2 x i1> @intrinsic_vmfeq_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f64_f64
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
|
|
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64.f64(
|
|
<vscale x 2 x double> %0,
|
|
double %1,
|
|
i64 %2)
|
|
|
|
ret <vscale x 2 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64.f64(
|
|
<vscale x 2 x i1>,
|
|
<vscale x 2 x double>,
|
|
double,
|
|
<vscale x 2 x i1>,
|
|
i64);
|
|
|
|
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f64_f64
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
|
|
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64.f64(
|
|
<vscale x 2 x i1> %0,
|
|
<vscale x 2 x double> %1,
|
|
double %2,
|
|
<vscale x 2 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret <vscale x 2 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64.f64(
|
|
<vscale x 4 x double>,
|
|
double,
|
|
i64);
|
|
|
|
define <vscale x 4 x i1> @intrinsic_vmfeq_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f64_f64
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
|
|
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64.f64(
|
|
<vscale x 4 x double> %0,
|
|
double %1,
|
|
i64 %2)
|
|
|
|
ret <vscale x 4 x i1> %a
|
|
}
|
|
|
|
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64.f64(
|
|
<vscale x 4 x i1>,
|
|
<vscale x 4 x double>,
|
|
double,
|
|
<vscale x 4 x i1>,
|
|
i64);
|
|
|
|
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f64_f64
|
|
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu
|
|
; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
|
|
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64.f64(
|
|
<vscale x 4 x i1> %0,
|
|
<vscale x 4 x double> %1,
|
|
double %2,
|
|
<vscale x 4 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret <vscale x 4 x i1> %a
|
|
}
|