forked from OSchip/llvm-project
128 lines
3.9 KiB
LLVM
128 lines
3.9 KiB
LLVM
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
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; RUN: --riscv-no-aliases < %s | FileCheck %s
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declare <vscale x 1 x i1> @llvm.riscv.vmandnot.nxv1i1(
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<vscale x 1 x i1>,
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<vscale x 1 x i1>,
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i64);
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define <vscale x 1 x i1> @intrinsic_vmandnot_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmandnot_mm_nxv1i1
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
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; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 1 x i1> @llvm.riscv.vmandnot.nxv1i1(
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<vscale x 1 x i1> %0,
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<vscale x 1 x i1> %1,
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i64 %2)
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ret <vscale x 1 x i1> %a
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}
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declare <vscale x 2 x i1> @llvm.riscv.vmandnot.nxv2i1(
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<vscale x 2 x i1>,
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<vscale x 2 x i1>,
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i64);
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define <vscale x 2 x i1> @intrinsic_vmandnot_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmandnot_mm_nxv2i1
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
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; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 2 x i1> @llvm.riscv.vmandnot.nxv2i1(
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<vscale x 2 x i1> %0,
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<vscale x 2 x i1> %1,
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i64 %2)
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ret <vscale x 2 x i1> %a
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}
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declare <vscale x 4 x i1> @llvm.riscv.vmandnot.nxv4i1(
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<vscale x 4 x i1>,
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<vscale x 4 x i1>,
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i64);
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define <vscale x 4 x i1> @intrinsic_vmandnot_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmandnot_mm_nxv4i1
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
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; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 4 x i1> @llvm.riscv.vmandnot.nxv4i1(
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<vscale x 4 x i1> %0,
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<vscale x 4 x i1> %1,
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i64 %2)
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ret <vscale x 4 x i1> %a
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}
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declare <vscale x 8 x i1> @llvm.riscv.vmandnot.nxv8i1(
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<vscale x 8 x i1>,
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<vscale x 8 x i1>,
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i64);
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define <vscale x 8 x i1> @intrinsic_vmandnot_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmandnot_mm_nxv8i1
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
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; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 8 x i1> @llvm.riscv.vmandnot.nxv8i1(
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<vscale x 8 x i1> %0,
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<vscale x 8 x i1> %1,
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i64 %2)
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ret <vscale x 8 x i1> %a
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}
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declare <vscale x 16 x i1> @llvm.riscv.vmandnot.nxv16i1(
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<vscale x 16 x i1>,
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<vscale x 16 x i1>,
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i64);
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define <vscale x 16 x i1> @intrinsic_vmandnot_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmandnot_mm_nxv16i1
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
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; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 16 x i1> @llvm.riscv.vmandnot.nxv16i1(
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<vscale x 16 x i1> %0,
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<vscale x 16 x i1> %1,
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i64 %2)
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ret <vscale x 16 x i1> %a
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}
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declare <vscale x 32 x i1> @llvm.riscv.vmandnot.nxv32i1(
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<vscale x 32 x i1>,
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<vscale x 32 x i1>,
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i64);
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define <vscale x 32 x i1> @intrinsic_vmandnot_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmandnot_mm_nxv32i1
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
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; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 32 x i1> @llvm.riscv.vmandnot.nxv32i1(
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<vscale x 32 x i1> %0,
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<vscale x 32 x i1> %1,
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i64 %2)
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ret <vscale x 32 x i1> %a
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}
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declare <vscale x 64 x i1> @llvm.riscv.vmandnot.nxv64i1(
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<vscale x 64 x i1>,
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<vscale x 64 x i1>,
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i64);
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define <vscale x 64 x i1> @intrinsic_vmandnot_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vmandnot_mm_nxv64i1
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
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; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 64 x i1> @llvm.riscv.vmandnot.nxv64i1(
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<vscale x 64 x i1> %0,
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<vscale x 64 x i1> %1,
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i64 %2)
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ret <vscale x 64 x i1> %a
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}
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