llvm-project/mlir/lib
Matthias Springer 7161aa06ef [mlir][linalg][bufferize] Reimplementation of scf.for bufferization
Instead of modifying the existing scf.for op, create a new op with memref OpOperands/OpResults and delete the old op.

New allocations / other memrefs can now be yielded from the loop. This functionality is deactivated by default and guarded against by AssertDestinationPassingStyle.

This change also introduces `replaceOp`, which will be utilized by all other `bufferize` implementations in future commits. Bufferization will then no longer rely on old (pre-bufferize) ops to DCE away. Instead old ops are deleted on the spot. This improves debuggability because there won't be any duplicate ops anymore (bufferized + not-yet-bufferized) when dumping IR during bufferization. It is also less fragile because unbufferized IR can no longer silently "hang around" due to an implementation bug.

Differential Revision: https://reviews.llvm.org/D114926
2021-12-15 18:29:22 +09:00
..
Analysis [MLIR] PresburgerSet subtraction: fix bug where the set `b` was not restored properly on return 2021-12-12 17:14:04 +05:30
Bindings/Python [mlir][python] Add fused location 2021-12-11 10:16:13 -08:00
CAPI [mlir][ExecutionEngine] Fix native dependencies for AsmParser and Printer 2021-12-13 21:12:12 +00:00
Conversion [mlir][linalg] Remove RangeOp and RangeType. 2021-12-15 07:19:10 +00:00
Dialect [mlir][linalg][bufferize] Reimplementation of scf.for bufferization 2021-12-15 18:29:22 +09:00
ExecutionEngine [mlir][sparse] speed up sparse tensor file I/O by more than 2x 2021-12-14 08:30:31 -08:00
IR [mlir][Vector] Patterns flattening vector transfers to 1D 2021-12-13 22:39:41 +00:00
Interfaces [mlir][Vector] Thread 0-d vectors through vector.transfer ops 2021-12-01 16:49:43 +00:00
Parser [mlir] Relax restriction on name location parsing 2021-12-12 08:06:59 -08:00
Pass Adjust "end namespace" comment in MLIR to match new agree'd coding style 2021-12-08 06:05:26 +00:00
Reducer Adjust "end namespace" comment in MLIR to match new agree'd coding style 2021-12-08 06:05:26 +00:00
Rewrite Adjust "end namespace" comment in MLIR to match new agree'd coding style 2021-12-08 06:05:26 +00:00
Support [mlir] Flag near misses in file splitting 2021-12-12 08:03:30 -08:00
TableGen Adjust "end namespace" comment in MLIR to match new agree'd coding style 2021-12-08 06:05:26 +00:00
Target [MLIR][GPU] Make max flat work group size for ROCDL kernels configurable 2021-12-14 20:12:23 +00:00
Tools [mlir][lsp] Use ResultGroupDefinition struct 2021-11-17 00:40:57 +00:00
Transforms [mlir] Split std.rank into tensor.rank and memref.rank. 2021-12-14 10:15:55 +01:00
Translation [mlir] run the verifier before translating a module 2021-07-28 18:15:58 +02:00
CMakeLists.txt Re-engineer MLIR python build support. 2021-07-27 15:54:58 +00:00