llvm-project/llvm/test/CodeGen/MIR/AArch64/atomic-memoperands.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
--- |
define void @atomic_memoperands() {
ret void
}
...
---
name: atomic_memoperands
body: |
bb.0:
; CHECK-LABEL: name: atomic_memoperands
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load unordered 8)
; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load monotonic 4)
; CHECK: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load acquire 2)
; CHECK: G_STORE [[LOAD2]](s16), [[COPY]](p0) :: (store release 2)
; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: (store acq_rel 4)
; CHECK: G_STORE [[LOAD]](s64), [[COPY]](p0) :: (store syncscope("singlethread") seq_cst 8)
; CHECK: RET_ReallyLR
%0:_(p0) = COPY %x0
%1:_(s64) = G_LOAD %0(p0) :: (load unordered 8)
%2:_(s32) = G_LOAD %0(p0) :: (load monotonic 4)
%3:_(s16) = G_LOAD %0(p0) :: (load acquire 2)
G_STORE %3(s16), %0(p0) :: (store release 2)
G_STORE %2(s32), %0(p0) :: (store acq_rel 4)
G_STORE %1(s64), %0(p0) :: (store syncscope("singlethread") seq_cst 8)
RET_ReallyLR
...