forked from OSchip/llvm-project
fa582b075c
Shadow stack solution introduces a new stack for return addresses only. The HW has a Shadow Stack Pointer (SSP) that points to the next return address. If we return to a different address, an exception is triggered. The shadow stack is managed using a series of intrinsics that are introduced in this patch as well as the new register (SSP). The intrinsics are mapped to new instruction set that implements CET mechanism. The patch also includes initial infrastructure support for IBT. For more information, please see the following: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf Differential Revision: https://reviews.llvm.org/D40223 Change-Id: I4daa1f27e88176be79a4ac3b4cd26a459e88fed4 llvm-svn: 318996 |
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AArch64 | ||
AMDGPU | ||
ARM | ||
Generic | ||
Hexagon | ||
Mips | ||
NVPTX | ||
PowerPC | ||
X86 | ||
README |
README
This directory contains tests for the MIR file format parser and printer. It was necessary to split the tests across different targets as no single target covers all features available in machine IR. Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As a rule of thumb this directory should only contain tests using 'llc -run-pass none'.