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llvm-project/llvm/test/CodeGen
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Craig Topper c2696d577b [X86] Use setcc ISD opcode for AVX512 integer comparisons all the way to isel 
I don't believe there is any real reason to have separate X86 specific opcodes for vector compares. Setcc has the same behavior just uses a different encoding for the condition code.

I had to change the CondCodeAction for SETLT and SETLE to prevent some transforms from changing SETGT lowering.

Differential Revision: https://reviews.llvm.org/D43608

llvm-svn: 335173
 		2018-06-20 21:05:02 +00:00
..
AArch64 [AArch64] Implement FLT_ROUNDS macro. 2018-06-20 12:09:01 +00:00
AMDGPU Allow binop C1, (select cc, CF, CT) -> select folding 2018-06-20 20:24:20 +00:00
ARC
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ARM ARM: convert ORR instructions to ADD where possible on Thumb. 2018-06-20 12:09:44 +00:00
AVR [AVR] Set trackLivenessAfterRegAlloc 2018-06-11 14:46:48 +00:00
BPF [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
Generic [DWARFv5] Tolerate files not all having an MD5 checksum. 2018-06-14 13:38:20 +00:00
Hexagon [Hexagon] Replace .ll test for expanding post-ra pesudos with .mir 2018-06-20 19:22:27 +00:00
Inputs
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Lanai Remove SETCCE use from Lanai's backend 2018-06-03 12:56:24 +00:00
MIR [MIRParser] Update a diagnostic message to use the correct register sigil. NFC 2018-06-19 18:39:40 +00:00
MSP430 Emit a left-shift instead of a power-of-two multiply for jump-tables 2018-05-16 08:58:26 +00:00
Mips [mips] Correct predicates for loads, bit manipulation instructions and some pseudos 2018-06-20 19:59:58 +00:00
NVPTX [DAG] fold FP binops with undef operands to NaN 2018-05-21 23:54:19 +00:00
Nios2
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PowerPC Allow binop C1, (select cc, CF, CT) -> select folding 2018-06-20 20:24:20 +00:00
RISCV [RISCV] Add tests for overflow intrinsics 2018-06-19 06:45:47 +00:00
SPARC [Sparc] Add support for 13-bit PIC 2018-06-11 05:50:08 +00:00
SystemZ [BranchFolding] Fix live-in's when hoisting code 2018-06-07 07:20:33 +00:00
Thumb [ARM] Testcase for Thumb1 cmp with constants. 2018-06-19 00:12:13 +00:00
Thumb2 ARM: convert ORR instructions to ADD where possible on Thumb. 2018-06-20 12:09:44 +00:00
WebAssembly [WebAssembly] Fix liveness tracking info after drop insertion 2018-06-19 20:30:42 +00:00
WinCFGuard
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WinEH [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
X86 [X86] Use setcc ISD opcode for AVX512 integer comparisons all the way to isel 2018-06-20 21:05:02 +00:00
XCore [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00