forked from OSchip/llvm-project
454 lines
16 KiB
C++
454 lines
16 KiB
C++
//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the VirtRegMap class.
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//
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// It also contains implementations of the Spiller interface, which, given a
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// virtual register map and a machine function, eliminates all virtual
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// references by replacing them with physical register references - adding spill
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// code as necessary.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "LiveDebugVariables.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SparseSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <algorithm>
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using namespace llvm;
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#define DEBUG_TYPE "regalloc"
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STATISTIC(NumSpillSlots, "Number of spill slots allocated");
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STATISTIC(NumIdCopies, "Number of identity moves eliminated after rewriting");
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//===----------------------------------------------------------------------===//
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// VirtRegMap implementation
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//===----------------------------------------------------------------------===//
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char VirtRegMap::ID = 0;
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INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
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bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
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MRI = &mf.getRegInfo();
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TII = mf.getSubtarget().getInstrInfo();
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TRI = mf.getSubtarget().getRegisterInfo();
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MF = &mf;
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Virt2PhysMap.clear();
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Virt2StackSlotMap.clear();
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Virt2SplitMap.clear();
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grow();
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return false;
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}
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void VirtRegMap::grow() {
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unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
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Virt2PhysMap.resize(NumRegs);
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Virt2StackSlotMap.resize(NumRegs);
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Virt2SplitMap.resize(NumRegs);
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}
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unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
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int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
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RC->getAlignment());
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++NumSpillSlots;
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return SS;
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}
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bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
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unsigned Hint = MRI->getSimpleHint(VirtReg);
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if (!Hint)
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return 0;
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if (TargetRegisterInfo::isVirtualRegister(Hint))
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Hint = getPhys(Hint);
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return getPhys(VirtReg) == Hint;
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}
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bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
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std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
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if (TargetRegisterInfo::isPhysicalRegister(Hint.second))
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return true;
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if (TargetRegisterInfo::isVirtualRegister(Hint.second))
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return hasPhys(Hint.second);
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return false;
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}
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int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
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assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
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"attempt to assign stack slot to already spilled register");
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const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
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return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
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}
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void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
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assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
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"attempt to assign stack slot to already spilled register");
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assert((SS >= 0 ||
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(SS >= MF->getFrameInfo()->getObjectIndexBegin())) &&
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"illegal fixed frame index");
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Virt2StackSlotMap[virtReg] = SS;
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}
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void VirtRegMap::print(raw_ostream &OS, const Module*) const {
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OS << "********** REGISTER MAP **********\n";
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for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
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OS << '[' << PrintReg(Reg, TRI) << " -> "
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<< PrintReg(Virt2PhysMap[Reg], TRI) << "] "
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<< TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
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}
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}
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for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
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OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
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<< "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
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}
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}
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OS << '\n';
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}
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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void VirtRegMap::dump() const {
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print(dbgs());
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}
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#endif
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//===----------------------------------------------------------------------===//
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// VirtRegRewriter
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//===----------------------------------------------------------------------===//
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//
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// The VirtRegRewriter is the last of the register allocator passes.
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// It rewrites virtual registers to physical registers as specified in the
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// VirtRegMap analysis. It also updates live-in information on basic blocks
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// according to LiveIntervals.
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//
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namespace {
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class VirtRegRewriter : public MachineFunctionPass {
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MachineFunction *MF;
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const TargetMachine *TM;
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const TargetRegisterInfo *TRI;
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const TargetInstrInfo *TII;
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MachineRegisterInfo *MRI;
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SlotIndexes *Indexes;
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LiveIntervals *LIS;
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VirtRegMap *VRM;
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SparseSet<unsigned> PhysRegs;
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void rewrite();
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void addMBBLiveIns();
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public:
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static char ID;
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VirtRegRewriter() : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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bool runOnMachineFunction(MachineFunction&) override;
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};
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} // end anonymous namespace
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char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
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INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
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"Virtual Register Rewriter", false, false)
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INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
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INITIALIZE_PASS_DEPENDENCY(LiveStacks)
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INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
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INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
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"Virtual Register Rewriter", false, false)
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char VirtRegRewriter::ID = 0;
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void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<LiveIntervals>();
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AU.addRequired<SlotIndexes>();
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AU.addPreserved<SlotIndexes>();
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AU.addRequired<LiveDebugVariables>();
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AU.addRequired<LiveStacks>();
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AU.addPreserved<LiveStacks>();
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AU.addRequired<VirtRegMap>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
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MF = &fn;
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TM = &MF->getTarget();
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TRI = MF->getSubtarget().getRegisterInfo();
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TII = MF->getSubtarget().getInstrInfo();
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MRI = &MF->getRegInfo();
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Indexes = &getAnalysis<SlotIndexes>();
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LIS = &getAnalysis<LiveIntervals>();
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VRM = &getAnalysis<VirtRegMap>();
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DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
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<< "********** Function: "
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<< MF->getName() << '\n');
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DEBUG(VRM->dump());
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// Add kill flags while we still have virtual registers.
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LIS->addKillFlags(VRM);
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// Live-in lists on basic blocks are required for physregs.
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addMBBLiveIns();
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// Rewrite virtual registers.
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rewrite();
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// Write out new DBG_VALUE instructions.
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getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
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// All machine operands and other references to virtual registers have been
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// replaced. Remove the virtual registers and release all the transient data.
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VRM->clearAllVirt();
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MRI->clearVirtRegs();
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return true;
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}
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// Compute MBB live-in lists from virtual register live ranges and their
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// assignments.
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void VirtRegRewriter::addMBBLiveIns() {
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SmallVector<MachineBasicBlock*, 16> LiveIn;
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for (unsigned Idx = 0, IdxE = MRI->getNumVirtRegs(); Idx != IdxE; ++Idx) {
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unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx);
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if (MRI->reg_nodbg_empty(VirtReg))
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continue;
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LiveInterval &LI = LIS->getInterval(VirtReg);
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if (LI.empty() || LIS->intervalIsInOneMBB(LI))
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continue;
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// This is a virtual register that is live across basic blocks. Its
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// assigned PhysReg must be marked as live-in to those blocks.
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unsigned PhysReg = VRM->getPhys(VirtReg);
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assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
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if (LI.hasSubRanges()) {
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for (LiveInterval::SubRange &S : LI.subranges()) {
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for (const auto &Seg : S.segments) {
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if (!Indexes->findLiveInMBBs(Seg.start, Seg.end, LiveIn))
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continue;
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for (MCSubRegIndexIterator SR(PhysReg, TRI); SR.isValid(); ++SR) {
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unsigned SubReg = SR.getSubReg();
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unsigned SubRegIndex = SR.getSubRegIndex();
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unsigned SubRegLaneMask = TRI->getSubRegIndexLaneMask(SubRegIndex);
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if ((SubRegLaneMask & S.LaneMask) == 0)
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continue;
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for (unsigned i = 0, e = LiveIn.size(); i != e; ++i) {
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LiveIn[i]->addLiveIn(SubReg);
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}
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}
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LiveIn.clear();
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}
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}
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} else {
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// Scan the segments of LI.
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for (const auto &Seg : LI.segments) {
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if (!Indexes->findLiveInMBBs(Seg.start, Seg.end, LiveIn))
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continue;
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for (unsigned i = 0, e = LiveIn.size(); i != e; ++i)
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LiveIn[i]->addLiveIn(PhysReg);
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LiveIn.clear();
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}
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}
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}
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// Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
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// each MBB's LiveIns set before calling addLiveIn on them.
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for (MachineBasicBlock &MBB : *MF)
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MBB.sortUniqueLiveIns();
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}
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void VirtRegRewriter::rewrite() {
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bool NoSubRegLiveness = !MRI->subRegLivenessEnabled();
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SmallVector<unsigned, 8> SuperDeads;
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SmallVector<unsigned, 8> SuperDefs;
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SmallVector<unsigned, 8> SuperKills;
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SmallPtrSet<const MachineInstr *, 4> NoReturnInsts;
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// Here we have a SparseSet to hold which PhysRegs are actually encountered
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// in the MF we are about to iterate over so that later when we call
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// setPhysRegUsed, we are only doing it for physRegs that were actually found
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// in the program and not for all of the possible physRegs for the given
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// target architecture. If the target has a lot of physRegs, then for a small
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// program there will be a significant compile time reduction here.
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PhysRegs.clear();
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PhysRegs.setUniverse(TRI->getNumRegs());
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// The function with uwtable should guarantee that the stack unwinder
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// can unwind the stack to the previous frame. Thus, we can't apply the
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// noreturn optimization if the caller function has uwtable attribute.
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bool HasUWTable = MF->getFunction()->hasFnAttribute(Attribute::UWTable);
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for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
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MBBI != MBBE; ++MBBI) {
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DEBUG(MBBI->print(dbgs(), Indexes));
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bool IsExitBB = MBBI->succ_empty();
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for (MachineBasicBlock::instr_iterator
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MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
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MachineInstr *MI = MII;
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++MII;
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// Check if this instruction is a call to a noreturn function. If this
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// is a call to noreturn function and we don't need the stack unwinding
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// functionality (i.e. this function does not have uwtable attribute and
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// the callee function has the nounwind attribute), then we can ignore
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// the definitions set by this instruction.
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if (!HasUWTable && IsExitBB && MI->isCall()) {
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for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
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MOE = MI->operands_end(); MOI != MOE; ++MOI) {
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MachineOperand &MO = *MOI;
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if (!MO.isGlobal())
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continue;
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const Function *Func = dyn_cast<Function>(MO.getGlobal());
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if (!Func || !Func->hasFnAttribute(Attribute::NoReturn) ||
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// We need to keep correct unwind information
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// even if the function will not return, since the
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// runtime may need it.
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!Func->hasFnAttribute(Attribute::NoUnwind))
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continue;
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NoReturnInsts.insert(MI);
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break;
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}
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}
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for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
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MOE = MI->operands_end(); MOI != MOE; ++MOI) {
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MachineOperand &MO = *MOI;
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// Make sure MRI knows about registers clobbered by regmasks.
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if (MO.isRegMask())
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MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
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// If we encounter a VirtReg or PhysReg then get at the PhysReg and add
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// it to the physreg bitset. Later we use only the PhysRegs that were
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// actually encountered in the MF to populate the MRI's used physregs.
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if (MO.isReg() && MO.getReg())
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PhysRegs.insert(
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TargetRegisterInfo::isVirtualRegister(MO.getReg()) ?
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VRM->getPhys(MO.getReg()) :
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MO.getReg());
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if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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continue;
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unsigned VirtReg = MO.getReg();
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unsigned PhysReg = VRM->getPhys(VirtReg);
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assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
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"Instruction uses unmapped VirtReg");
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assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
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// Preserve semantics of sub-register operands.
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if (MO.getSubReg()) {
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// A virtual register kill refers to the whole register, so we may
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// have to add <imp-use,kill> operands for the super-register. A
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// partial redef always kills and redefines the super-register.
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if (NoSubRegLiveness && MO.readsReg()
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&& (MO.isDef() || MO.isKill()))
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SuperKills.push_back(PhysReg);
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if (MO.isDef()) {
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// The <def,undef> flag only makes sense for sub-register defs, and
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// we are substituting a full physreg. An <imp-use,kill> operand
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// from the SuperKills list will represent the partial read of the
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// super-register.
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MO.setIsUndef(false);
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// Also add implicit defs for the super-register.
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if (NoSubRegLiveness) {
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if (MO.isDead())
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SuperDeads.push_back(PhysReg);
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else
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SuperDefs.push_back(PhysReg);
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}
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}
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// PhysReg operands cannot have subregister indexes.
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PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
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assert(PhysReg && "Invalid SubReg for physical register");
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MO.setSubReg(0);
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}
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// Rewrite. Note we could have used MachineOperand::substPhysReg(), but
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// we need the inlining here.
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MO.setReg(PhysReg);
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}
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// Add any missing super-register kills after rewriting the whole
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// instruction.
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while (!SuperKills.empty())
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MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
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while (!SuperDeads.empty())
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MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
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while (!SuperDefs.empty())
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MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
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DEBUG(dbgs() << "> " << *MI);
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// Finally, remove any identity copies.
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if (MI->isIdentityCopy()) {
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++NumIdCopies;
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DEBUG(dbgs() << "Deleting identity copy.\n");
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if (Indexes)
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Indexes->removeMachineInstrFromMaps(MI);
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// It's safe to erase MI because MII has already been incremented.
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MI->eraseFromParent();
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}
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}
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}
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// Tell MRI about physical registers in use.
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if (NoReturnInsts.empty()) {
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for (SparseSet<unsigned>::iterator
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RegI = PhysRegs.begin(), E = PhysRegs.end(); RegI != E; ++RegI)
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if (!MRI->reg_nodbg_empty(*RegI))
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MRI->setPhysRegUsed(*RegI);
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} else {
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for (SparseSet<unsigned>::iterator
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I = PhysRegs.begin(), E = PhysRegs.end(); I != E; ++I) {
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unsigned Reg = *I;
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if (MRI->reg_nodbg_empty(Reg))
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continue;
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// Check if this register has a use that will impact the rest of the
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// code. Uses in debug and noreturn instructions do not impact the
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// generated code.
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for (MachineInstr &It : MRI->reg_nodbg_instructions(Reg)) {
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if (!NoReturnInsts.count(&It)) {
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MRI->setPhysRegUsed(Reg);
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break;
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}
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}
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}
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}
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}
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