forked from OSchip/llvm-project
182 lines
5.8 KiB
C++
182 lines
5.8 KiB
C++
//=- AArch64RedundantCopyElimination.cpp - Remove useless copy for AArch64 -=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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// This pass removes unnecessary zero copies in BBs that are targets of
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// cbz/cbnz instructions. For instance, the copy instruction in the code below
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// can be removed because the CBZW jumps to BB#2 when W0 is zero.
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// BB#1:
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// CBZW %W0, <BB#2>
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// BB#2:
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// %W0 = COPY %WZR
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// This pass should be run after register allocation.
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//
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// FIXME: This should be extended to handle any constant other than zero. E.g.,
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// cmp w0, #1
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// b.eq .BB1
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// BB1:
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// mov w0, #1
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//
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// FIXME: This could also be extended to check the whole dominance subtree below
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// the comparison if the compile time regression is acceptable.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-copyelim"
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STATISTIC(NumCopiesRemoved, "Number of copies removed.");
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namespace {
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class AArch64RedundantCopyElimination : public MachineFunctionPass {
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const MachineRegisterInfo *MRI;
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const TargetRegisterInfo *TRI;
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public:
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static char ID;
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AArch64RedundantCopyElimination() : MachineFunctionPass(ID) {
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initializeAArch64RedundantCopyEliminationPass(
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*PassRegistry::getPassRegistry());
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}
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bool optimizeCopy(MachineBasicBlock *MBB);
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bool runOnMachineFunction(MachineFunction &MF) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::AllVRegsAllocated);
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}
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const char *getPassName() const override {
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return "AArch64 Redundant Copy Elimination";
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}
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};
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char AArch64RedundantCopyElimination::ID = 0;
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}
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INITIALIZE_PASS(AArch64RedundantCopyElimination, "aarch64-copyelim",
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"AArch64 redundant copy elimination pass", false, false)
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static bool guaranteesZeroRegInBlock(MachineInstr &MI, MachineBasicBlock *MBB) {
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unsigned Opc = MI.getOpcode();
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// Check if the current basic block is the target block to which the
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// CBZ/CBNZ instruction jumps when its Wt/Xt is zero.
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if ((Opc == AArch64::CBZW || Opc == AArch64::CBZX) &&
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MBB == MI.getOperand(1).getMBB())
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return true;
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else if ((Opc == AArch64::CBNZW || Opc == AArch64::CBNZX) &&
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MBB != MI.getOperand(1).getMBB())
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return true;
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return false;
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}
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bool AArch64RedundantCopyElimination::optimizeCopy(MachineBasicBlock *MBB) {
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// Check if the current basic block has a single predecessor.
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if (MBB->pred_size() != 1)
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return false;
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MachineBasicBlock *PredMBB = *MBB->pred_begin();
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MachineBasicBlock::iterator CompBr = PredMBB->getLastNonDebugInstr();
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if (CompBr == PredMBB->end() || PredMBB->succ_size() != 2)
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return false;
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++CompBr;
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do {
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--CompBr;
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if (guaranteesZeroRegInBlock(*CompBr, MBB))
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break;
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} while (CompBr != PredMBB->begin() && CompBr->isTerminator());
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// We've not found a CBZ/CBNZ, time to bail out.
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if (!guaranteesZeroRegInBlock(*CompBr, MBB))
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return false;
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unsigned TargetReg = CompBr->getOperand(0).getReg();
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if (!TargetReg)
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return false;
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assert(TargetRegisterInfo::isPhysicalRegister(TargetReg) &&
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"Expect physical register");
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// Remember all registers aliasing with TargetReg.
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SmallSetVector<unsigned, 8> TargetRegs;
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for (MCRegAliasIterator AI(TargetReg, TRI, true); AI.isValid(); ++AI)
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TargetRegs.insert(*AI);
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bool Changed = false;
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MachineBasicBlock::iterator LastChange = MBB->begin();
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unsigned SmallestDef = TargetReg;
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// Remove redundant Copy instructions unless TargetReg is modified.
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;) {
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MachineInstr *MI = &*I;
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++I;
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if (MI->isCopy() && MI->getOperand(0).isReg() &&
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MI->getOperand(1).isReg()) {
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unsigned DefReg = MI->getOperand(0).getReg();
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unsigned SrcReg = MI->getOperand(1).getReg();
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if ((SrcReg == AArch64::XZR || SrcReg == AArch64::WZR) &&
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!MRI->isReserved(DefReg) &&
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(TargetReg == DefReg || TRI->isSuperRegister(DefReg, TargetReg))) {
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DEBUG(dbgs() << "Remove redundant Copy : ");
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DEBUG((MI)->print(dbgs()));
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MI->eraseFromParent();
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Changed = true;
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LastChange = I;
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NumCopiesRemoved++;
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SmallestDef =
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TRI->isSubRegister(SmallestDef, DefReg) ? DefReg : SmallestDef;
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continue;
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}
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}
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if (MI->modifiesRegister(TargetReg, TRI))
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break;
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}
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if (!Changed)
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return false;
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// Otherwise, we have to fixup the use-def chain, starting with the
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// CBZ/CBNZ. Conservatively mark as much as we can live.
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CompBr->clearRegisterKills(SmallestDef, TRI);
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if (std::none_of(TargetRegs.begin(), TargetRegs.end(),
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[&](unsigned Reg) { return MBB->isLiveIn(Reg); }))
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MBB->addLiveIn(TargetReg);
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// Clear any kills of TargetReg between CompBr and the last removed COPY.
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for (MachineInstr &MMI :
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make_range(MBB->begin()->getIterator(), LastChange->getIterator()))
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MMI.clearRegisterKills(SmallestDef, TRI);
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return true;
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}
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bool AArch64RedundantCopyElimination::runOnMachineFunction(
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MachineFunction &MF) {
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if (skipFunction(*MF.getFunction()))
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return false;
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TRI = MF.getSubtarget().getRegisterInfo();
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MRI = &MF.getRegInfo();
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF)
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Changed |= optimizeCopy(&MBB);
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return Changed;
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}
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FunctionPass *llvm::createAArch64RedundantCopyEliminationPass() {
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return new AArch64RedundantCopyElimination();
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}
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