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AsmParser
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Add unittests to {ARM | AArch64}TargetParser.
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2016-07-28 06:11:18 +00:00 |
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Disassembler
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Minor code cleanups. NFC.
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2016-07-15 22:42:52 +00:00 |
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InstPrinter
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AArch64: TableGenerate system instruction operands.
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2016-07-05 21:23:04 +00:00 |
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MCTargetDesc
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MC] Provide an MCTargetOptions to implementors of MCAsmBackendCtorTy, NFC
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2016-07-25 17:18:28 +00:00 |
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TargetInfo
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Remove autoconf support
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2016-01-26 21:29:08 +00:00 |
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Utils
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AArch64: try to fix optimized build failure.
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2016-07-05 23:15:58 +00:00 |
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AArch64.h
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[AArch64] Register passes so they can be run by llc
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2016-08-01 05:56:57 +00:00 |
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AArch64.td
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[AArch64] Add support for Samsung Exynos M2 (NFC).
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2016-08-01 18:39:45 +00:00 |
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AArch64A53Fix835769.cpp
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[AArch64] Register passes so they can be run by llc
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2016-08-01 05:56:57 +00:00 |
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AArch64A57FPLoadBalancing.cpp
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[AArch64] Register passes so they can be run by llc
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2016-08-01 05:56:57 +00:00 |
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AArch64AddressTypePromotion.cpp
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[AArch64] Register passes so they can be run by llc
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2016-08-01 05:56:57 +00:00 |
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AArch64AdvSIMDScalarPass.cpp
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[AArch64] Register passes so they can be run by llc
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2016-08-01 05:56:57 +00:00 |
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AArch64AsmPrinter.cpp
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AArch64: Change modeling of zero cycle zeroing.
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2016-07-06 21:39:33 +00:00 |
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AArch64BranchRelaxation.cpp
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AArch64: Consolidate branch inversion logic
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2016-08-02 08:30:06 +00:00 |
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AArch64CallLowering.cpp
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GlobalISel: IRTranslate PHI instructions
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2016-08-05 17:16:40 +00:00 |
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AArch64CallLowering.h
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[GlobalISel] Coding style and whitespace fixes
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2016-04-14 17:23:33 +00:00 |
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AArch64CallingConvention.h
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Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef.
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2015-12-05 07:13:35 +00:00 |
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AArch64CallingConvention.td
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GlobalISel[AArch64]: support pointer types in argument lowering.
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2016-07-25 21:01:17 +00:00 |
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AArch64CleanupLocalDynamicTLSPass.cpp
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[AArch64] Register passes so they can be run by llc
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2016-08-01 05:56:57 +00:00 |
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AArch64CollectLOH.cpp
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[AArch64] Register passes so they can be run by llc
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2016-08-01 05:56:57 +00:00 |
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AArch64ConditionOptimizer.cpp
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[AArch64] Register passes so they can be run by llc
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2016-08-01 05:56:57 +00:00 |
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AArch64ConditionalCompares.cpp
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[AArch64] Register passes so they can be run by llc
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2016-08-01 05:56:57 +00:00 |
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AArch64DeadRegisterDefinitionsPass.cpp
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[AArch64] Register passes so they can be run by llc
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2016-08-01 05:56:57 +00:00 |
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AArch64ExpandPseudoInsts.cpp
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[AArch64] Register AArch64LoadStoreOptimizer so it can be run by llc -run-pass. NFCI.
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2016-07-20 21:45:58 +00:00 |
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AArch64FastISel.cpp
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AArch64: properly calculate cmpxchg status in FastISel.
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2016-08-02 20:22:36 +00:00 |
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AArch64FrameLowering.cpp
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MachineFunction: Return reference for getFrameInfo(); NFC
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2016-07-28 18:40:00 +00:00 |
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AArch64FrameLowering.h
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[PEI, AArch64] Use empty spaces in stack area for local stack slot allocation.
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2016-06-02 16:22:07 +00:00 |
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AArch64ISelDAGToDAG.cpp
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AArch64: TableGenerate system instruction operands.
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2016-07-05 21:23:04 +00:00 |
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AArch64ISelLowering.cpp
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AArch64: don't assume all i128s are BUILD_PAIRs
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2016-08-04 19:32:28 +00:00 |
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AArch64ISelLowering.h
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MachineFunction: Return reference for getFrameInfo(); NFC
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2016-07-28 18:40:00 +00:00 |
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AArch64InstrAtomics.td
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AArch64: properly calculate cmpxchg status in FastISel.
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2016-08-02 20:22:36 +00:00 |
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AArch64InstrFormats.td
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AArch64: TableGenerate system instruction operands.
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2016-07-05 21:23:04 +00:00 |
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AArch64InstrInfo.cpp
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AArch64: Assert on branch displacement bits
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2016-08-02 08:56:52 +00:00 |
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AArch64InstrInfo.h
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AArch64: BranchRelaxtion cleanups
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2016-08-02 08:06:17 +00:00 |
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AArch64InstrInfo.td
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AArch64: Change modeling of zero cycle zeroing.
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2016-07-06 21:39:33 +00:00 |
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AArch64InstructionSelector.cpp
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[AArch64][GlobalISel] Select G_XOR.
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2016-07-29 16:56:25 +00:00 |
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AArch64InstructionSelector.h
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[GlobalISel] Introduce an instruction selector.
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2016-07-27 14:31:55 +00:00 |
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AArch64LoadStoreOptimizer.cpp
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[AArch64] Load/store opt: Don't count transient instructions towards search limits.
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2016-07-21 15:20:25 +00:00 |
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AArch64MCInstLower.cpp
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Convert some AArch64 code to foreach loops. NFC.
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2015-08-03 19:04:32 +00:00 |
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AArch64MCInstLower.h
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…
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AArch64MachineFunctionInfo.h
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[AArch64] Mark various *Info classes as 'final'. NFC.
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2016-07-27 14:31:46 +00:00 |
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AArch64MachineLegalizer.cpp
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GlobalISel: extend add widening to SUB, MUL, OR, AND and XOR.
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2016-08-04 21:39:49 +00:00 |
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AArch64MachineLegalizer.h
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Fix include case. NFC.
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2016-07-22 20:15:19 +00:00 |
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AArch64PBQPRegAlloc.cpp
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CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC
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2016-02-27 06:40:41 +00:00 |
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AArch64PBQPRegAlloc.h
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…
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AArch64PerfectShuffle.h
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…
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AArch64PromoteConstant.cpp
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[AArch64] Register passes so they can be run by llc
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2016-08-01 05:56:57 +00:00 |
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AArch64RedundantCopyElimination.cpp
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[AArch64] Register passes so they can be run by llc
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2016-08-01 05:56:57 +00:00 |
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AArch64RegisterBankInfo.cpp
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GlobalISel: implement low-level type with just size & vector lanes.
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2016-07-20 19:09:30 +00:00 |
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AArch64RegisterBankInfo.h
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[AArch64] Mark various *Info classes as 'final'. NFC.
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2016-07-27 14:31:46 +00:00 |
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AArch64RegisterInfo.cpp
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MachineFunction: Return reference for getFrameInfo(); NFC
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2016-07-28 18:40:00 +00:00 |
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AArch64RegisterInfo.h
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[AArch64] Mark various *Info classes as 'final'. NFC.
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2016-07-27 14:31:46 +00:00 |
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AArch64RegisterInfo.td
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Fix typo in comment. NFC
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2016-04-24 17:55:57 +00:00 |
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AArch64SchedA53.td
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Remove MinLatency in SchedMachineModel. NFC.
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2016-04-26 00:37:46 +00:00 |
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AArch64SchedA57.td
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AArch64: Reenable CompleteModel for A53, A57 and Kryo models
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2016-03-01 21:55:35 +00:00 |
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AArch64SchedA57WriteRes.td
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…
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AArch64SchedCyclone.td
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CodeGen: Use MachineInstr& in TargetInstrInfo, NFC
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2016-06-30 00:01:54 +00:00 |
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AArch64SchedKryo.td
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AArch64: Reenable CompleteModel for A53, A57 and Kryo models
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2016-03-01 21:55:35 +00:00 |
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AArch64SchedKryoDetails.td
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[AArch64] Add support for Qualcomm Kryo CPU.
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2016-02-12 15:51:51 +00:00 |
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AArch64SchedM1.td
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[AArch64] Adjust the model for the vector by element FP multiplies on Exynos M1. (NFC)
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2016-06-24 18:58:54 +00:00 |
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AArch64SchedVulcan.td
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[AArch64] Add Broadcom Vulcan scheduling model.
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2016-06-30 06:42:31 +00:00 |
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AArch64Schedule.td
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CodeGen: Use MachineInstr& in TargetInstrInfo, NFC
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2016-06-30 00:01:54 +00:00 |
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AArch64SelectionDAGInfo.cpp
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[SDAG] Remove FixedArgs parameter from CallLoweringInfo::setCallee
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2016-06-22 12:54:25 +00:00 |
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AArch64SelectionDAGInfo.h
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Pass DebugLoc and SDLoc by const ref.
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2016-06-12 15:39:02 +00:00 |
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AArch64StorePairSuppress.cpp
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[AArch64] Register passes so they can be run by llc
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2016-08-01 05:56:57 +00:00 |
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AArch64Subtarget.cpp
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[GlobalISel] Introduce an instruction selector.
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2016-07-27 14:31:55 +00:00 |
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AArch64Subtarget.h
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[GlobalISel] Introduce an instruction selector.
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2016-07-27 14:31:55 +00:00 |
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AArch64SystemOperands.td
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AArch64: TableGenerate system instruction operands.
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2016-07-05 21:23:04 +00:00 |
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AArch64TargetMachine.cpp
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[AArch64] Register passes so they can be run by llc
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2016-08-01 05:56:57 +00:00 |
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AArch64TargetMachine.h
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Delete Reloc::Default.
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2016-05-18 22:04:49 +00:00 |
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AArch64TargetObjectFile.cpp
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…
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AArch64TargetObjectFile.h
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…
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AArch64TargetTransformInfo.cpp
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AArch64: Do not test for CPUs, use SubtargetFeatures
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2016-06-02 18:03:53 +00:00 |
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AArch64TargetTransformInfo.h
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[TTI] Add hook for vector extract with extension
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2016-04-27 15:20:21 +00:00 |
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CMakeLists.txt
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[GlobalISel] Introduce an instruction selector.
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2016-07-27 14:31:55 +00:00 |
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LLVMBuild.txt
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[AArch64] Plug the beginning of the GlobalISel pipeline.
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2016-02-11 19:35:06 +00:00 |
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