forked from OSchip/llvm-project
162 lines
6.9 KiB
LLVM
162 lines
6.9 KiB
LLVM
; RUN: opt %loadPolly -polly-scops \
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; RUN: -polly-allow-nonaffine -polly-allow-nonaffine-branches \
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; RUN: -polly-allow-nonaffine-loops -analyze < %s | FileCheck %s
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; RUN: opt %loadPolly -polly-scops -polly-allow-nonaffine \
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; RUN: -polly-process-unprofitable=false \
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; RUN: -polly-allow-nonaffine-branches -polly-allow-nonaffine-loops \
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; RUN: -analyze < %s | FileCheck %s --check-prefix=PROFIT
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;
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; Verify that we over approximate the read acces of A[j] in the last statement as j is
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; computed in a non-affine loop we do not model.
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;
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; CHECK: Function: f
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; CHECK-NEXT: Region: %bb2---%bb24
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; CHECK-NEXT: Max Loop Depth: 1
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; CHECK-NEXT: Invariant Accesses: {
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; CHECK-NEXT: }
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; CHECK-NEXT: Context:
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; CHECK-NEXT: [N] -> { : -2147483648 <= N <= 2147483647 }
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; CHECK-NEXT: Assumed Context:
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; CHECK-NEXT: [N] -> { : }
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; CHECK-NEXT: Invalid Context:
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; CHECK-NEXT: [N] -> { : 1 = 0 }
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; CHECK-NEXT: p0: %N
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; CHECK-NEXT: Arrays {
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; CHECK-NEXT: i32 MemRef_j_0__phi; // Element size 4
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; CHECK-NEXT: i32 MemRef_j_0; // Element size 4
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; CHECK-NEXT: i32 MemRef_A[*]; // Element size 4
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; CHECK-NEXT: i32 MemRef_j_2__phi; // Element size 4
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; CHECK-NEXT: i32 MemRef_j_2; // Element size 4
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; CHECK-NEXT: }
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; CHECK-NEXT: Arrays (Bounds as pw_affs) {
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; CHECK-NEXT: i32 MemRef_j_0__phi; // Element size 4
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; CHECK-NEXT: i32 MemRef_j_0; // Element size 4
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; CHECK-NEXT: i32 MemRef_A[*]; // Element size 4
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; CHECK-NEXT: i32 MemRef_j_2__phi; // Element size 4
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; CHECK-NEXT: i32 MemRef_j_2; // Element size 4
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; CHECK-NEXT: }
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; CHECK-NEXT: Alias Groups (0):
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; CHECK-NEXT: n/a
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; CHECK-NEXT: Statements {
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; CHECK-NEXT: Stmt_bb2
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; CHECK-NEXT: Domain :=
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; CHECK-NEXT: [N] -> { Stmt_bb2[i0] : 0 <= i0 <= N; Stmt_bb2[0] : N < 0 };
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; CHECK-NEXT: Schedule :=
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; CHECK-NEXT: [N] -> { Stmt_bb2[i0] -> [i0, 0] : i0 <= N; Stmt_bb2[0] -> [0, 0] : N < 0 };
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK-NEXT: [N] -> { Stmt_bb2[i0] -> MemRef_j_0__phi[] };
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK-NEXT: [N] -> { Stmt_bb2[i0] -> MemRef_j_0[] };
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; CHECK-NEXT: Stmt_bb4__TO__bb18
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; CHECK-NEXT: Domain :=
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; CHECK-NEXT: [N] -> { Stmt_bb4__TO__bb18[i0] : 0 <= i0 < N };
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; CHECK-NEXT: Schedule :=
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; CHECK-NEXT: [N] -> { Stmt_bb4__TO__bb18[i0] -> [i0, 1] };
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_A[i0] };
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_A[i0] };
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; CHECK-NEXT: MayWriteAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_A[i0] };
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK-NEXT: [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_j_2__phi[] };
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK-NEXT: [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_j_0[] };
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; CHECK-NEXT: Stmt_bb18
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; CHECK-NEXT: Domain :=
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; CHECK-NEXT: [N] -> { Stmt_bb18[i0] : 0 <= i0 < N };
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; CHECK-NEXT: Schedule :=
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; CHECK-NEXT: [N] -> { Stmt_bb18[i0] -> [i0, 2] };
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK-NEXT: [N] -> { Stmt_bb18[i0] -> MemRef_j_2[] };
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK-NEXT: [N] -> { Stmt_bb18[i0] -> MemRef_j_2__phi[] };
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: [N] -> { Stmt_bb18[i0] -> MemRef_A[o0] : -2147483648 <= o0 <= 2147483647 };
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: [N] -> { Stmt_bb18[i0] -> MemRef_A[i0] };
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; CHECK-NEXT: Stmt_bb23
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; CHECK-NEXT: Domain :=
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; CHECK-NEXT: [N] -> { Stmt_bb23[i0] : 0 <= i0 < N };
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; CHECK-NEXT: Schedule :=
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; CHECK-NEXT: [N] -> { Stmt_bb23[i0] -> [i0, 3] };
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK-NEXT: [N] -> { Stmt_bb23[i0] -> MemRef_j_2[] };
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK-NEXT: [N] -> { Stmt_bb23[i0] -> MemRef_j_0__phi[] };
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; CHECK-NEXT: }
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;
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; Due to the scalar accesses we are not able to distribute the outer loop, thus we do not consider the region profitable.
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;
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; PROFIT-NOT: Statements
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;
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; void f(int *A, int N, int M) {
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; int i = 0, j = 0;
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; for (i = 0; i < N; i++) {
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; if (A[i])
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; for (j = 0; j < M; j++)
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; A[i]++;
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; A[i] = A[j];
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; }
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; }
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;
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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define void @f(i32* %A, i32 %N, i32 %M) {
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bb:
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%tmp = icmp sgt i32 %M, 0
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%smax = select i1 %tmp, i32 %M, i32 0
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%tmp1 = sext i32 %N to i64
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br label %bb2
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bb2: ; preds = %bb23, %bb
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%indvars.iv = phi i64 [ %indvars.iv.next, %bb23 ], [ 0, %bb ]
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%j.0 = phi i32 [ 0, %bb ], [ %j.2, %bb23 ]
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%tmp3 = icmp slt i64 %indvars.iv, %tmp1
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br i1 %tmp3, label %bb4, label %bb24
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bb4: ; preds = %bb2
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%tmp5 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
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%tmp6 = load i32, i32* %tmp5, align 4
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%tmp7 = icmp eq i32 %tmp6, 0
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br i1 %tmp7, label %bb18, label %bb8
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bb8: ; preds = %bb4
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br label %bb9
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bb9: ; preds = %bb15, %bb8
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%j.1 = phi i32 [ 0, %bb8 ], [ %tmp16, %bb15 ]
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%tmp10 = icmp slt i32 %j.1, %M
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br i1 %tmp10, label %bb11, label %bb17
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bb11: ; preds = %bb9
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%tmp12 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
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%tmp13 = load i32, i32* %tmp12, align 4
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%tmp14 = add nsw i32 %tmp13, 1
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store i32 %tmp14, i32* %tmp12, align 4
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br label %bb15
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bb15: ; preds = %bb11
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%tmp16 = add nuw nsw i32 %j.1, 1
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br label %bb9
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bb17: ; preds = %bb9
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br label %bb18
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bb18: ; preds = %bb4, %bb17
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%j.2 = phi i32 [ %smax, %bb17 ], [ %j.0, %bb4 ]
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%tmp19 = sext i32 %j.2 to i64
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%tmp20 = getelementptr inbounds i32, i32* %A, i64 %tmp19
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%tmp21 = load i32, i32* %tmp20, align 4
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%tmp22 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
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store i32 %tmp21, i32* %tmp22, align 4
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br label %bb23
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bb23: ; preds = %bb18
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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br label %bb2
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bb24: ; preds = %bb2
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ret void
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}
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