llvm-project/llvm/test/CodeGen/RISCV
Alex Bradbury dc31c61b18 [RISCV] Add custom CC_RISCV calling convention and improved call support
The TableGen-based calling convention definitions are inflexible, while
writing a function to implement the calling convention is very
straight-forward, and allows difficult cases to be handled more easily. With
this patch adds support for:
* Passing large scalars according to the RV32I calling convention
* Byval arguments
* Passing values on the stack when the argument registers are exhausted

The custom CC_RISCV calling convention is also used for returns.

This patch also documents the ABI lowering that a language frontend is 
expected to perform. I would like to work to simplify these requirements over 
time, but this will require further discussion within the LLVM community.

We add PendingArgFlags CCState, as a companion to PendingLocs.

The PendingLocs vector is used by a number of backends to handle arguments 
that are split during legalisation. However CCValAssign doesn't keep track of 
the original argument alignment. Therefore, add a PendingArgFlags vector which 
can be used to keep track of the ISD::ArgFlagsTy for every value added to 
PendingLocs.

Differential Revision: https://reviews.llvm.org/D39898

llvm-svn: 320359
2017-12-11 12:49:02 +00:00
..
addc-adde-sube-subc.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
alloca.ll [RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestore 2017-12-11 12:38:17 +00:00
alu32.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
bare-select.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
blockaddress.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
branch.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
bswap-ctlz-cttz-ctpop.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
byval.ll [RISCV] Add custom CC_RISCV calling convention and improved call support 2017-12-11 12:49:02 +00:00
calling-conv-sext-zext.ll [RISCV] Add custom CC_RISCV calling convention and improved call support 2017-12-11 12:49:02 +00:00
calling-conv.ll [RISCV] Add custom CC_RISCV calling convention and improved call support 2017-12-11 12:49:02 +00:00
calls.ll [RISCV] Add custom CC_RISCV calling convention and improved call support 2017-12-11 12:49:02 +00:00
div.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
fp128.ll [RISCV] Add custom CC_RISCV calling convention and improved call support 2017-12-11 12:49:02 +00:00
frame.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
i32-icmp.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
imm.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
indirectbr.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
jumptable.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
lit.local.cfg
mem.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
mul.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
rem.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
rotl-rotr.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
select-cc.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
sext-zext-trunc.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
shifts.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
wide-mem.ll [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00