forked from OSchip/llvm-project
af91e7e6d2
This patch enables fusing dependent AESE/AESMC and AESD/AESIMC instruction pairs on Cortex-A72, as recommended in the Software Optimization Guide, section 4.10. llvm-svn: 303073 |
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Hexagon | ||
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Lanai | ||
MIR | ||
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XCore |