forked from OSchip/llvm-project
316 lines
10 KiB
LLVM
316 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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; fold (mul x, 0) -> 0
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define <4 x i32> @combine_vec_mul_zero(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_zero:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_zero:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = mul <4 x i32> %x, zeroinitializer
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ret <4 x i32> %1
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}
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; fold (mul x, 1) -> x
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define <4 x i32> @combine_vec_mul_one(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_one:
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; SSE: # %bb.0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_one:
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; AVX: # %bb.0:
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; AVX-NEXT: retq
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%1 = mul <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %1
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}
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; fold (mul x, -1) -> 0-x
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define <4 x i32> @combine_vec_mul_negone(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_negone:
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; SSE: # %bb.0:
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; SSE-NEXT: pxor %xmm1, %xmm1
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; SSE-NEXT: psubd %xmm0, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_negone:
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; AVX: # %bb.0:
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; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = mul <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %1
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}
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; fold (mul x, (1 << c)) -> x << c
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define <4 x i32> @combine_vec_mul_pow2a(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_pow2a:
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; SSE: # %bb.0:
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; SSE-NEXT: paddd %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_pow2a:
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; AVX: # %bb.0:
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; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = mul <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_mul_pow2b(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_pow2b:
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; SSE: # %bb.0:
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_pow2b:
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; AVX: # %bb.0:
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; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = mul <4 x i32> %x, <i32 1, i32 2, i32 4, i32 16>
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ret <4 x i32> %1
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}
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define <4 x i64> @combine_vec_mul_pow2c(<4 x i64> %x) {
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; SSE-LABEL: combine_vec_mul_pow2c:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm2
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; SSE-NEXT: psllq $1, %xmm2
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; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm0[0,1,2,3],xmm2[4,5,6,7]
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: psllq $4, %xmm0
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; SSE-NEXT: psllq $2, %xmm1
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; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5,6,7]
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; SSE-NEXT: movdqa %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_pow2c:
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; AVX: # %bb.0:
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; AVX-NEXT: vpsllvq {{.*}}(%rip), %ymm0, %ymm0
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; AVX-NEXT: retq
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%1 = mul <4 x i64> %x, <i64 1, i64 2, i64 4, i64 16>
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ret <4 x i64> %1
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}
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; fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
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define <4 x i32> @combine_vec_mul_negpow2a(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_negpow2a:
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; SSE: # %bb.0:
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; SSE-NEXT: paddd %xmm0, %xmm0
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; SSE-NEXT: pxor %xmm1, %xmm1
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; SSE-NEXT: psubd %xmm0, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_negpow2a:
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; AVX: # %bb.0:
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; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = mul <4 x i32> %x, <i32 -2, i32 -2, i32 -2, i32 -2>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_mul_negpow2b(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_negpow2b:
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; SSE: # %bb.0:
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_negpow2b:
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; AVX: # %bb.0:
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; AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = mul <4 x i32> %x, <i32 -1, i32 -2, i32 -4, i32 -16>
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ret <4 x i32> %1
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}
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define <4 x i64> @combine_vec_mul_negpow2c(<4 x i64> %x) {
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; SSE-LABEL: combine_vec_mul_negpow2c:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa {{.*#+}} xmm2 = [4294967295,4294967295]
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; SSE-NEXT: movdqa %xmm0, %xmm3
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; SSE-NEXT: pmuludq %xmm2, %xmm3
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; SSE-NEXT: movdqa %xmm0, %xmm4
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; SSE-NEXT: psrlq $32, %xmm4
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; SSE-NEXT: movdqa {{.*#+}} xmm5 = [18446744073709551615,18446744073709551614]
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; SSE-NEXT: pmuludq %xmm5, %xmm4
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; SSE-NEXT: paddq %xmm3, %xmm4
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; SSE-NEXT: psllq $32, %xmm4
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; SSE-NEXT: pmuludq %xmm5, %xmm0
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; SSE-NEXT: paddq %xmm4, %xmm0
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; SSE-NEXT: pmuludq %xmm1, %xmm2
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; SSE-NEXT: movdqa %xmm1, %xmm3
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; SSE-NEXT: psrlq $32, %xmm3
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; SSE-NEXT: movdqa {{.*#+}} xmm4 = [18446744073709551612,18446744073709551600]
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; SSE-NEXT: pmuludq %xmm4, %xmm3
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; SSE-NEXT: paddq %xmm2, %xmm3
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; SSE-NEXT: psllq $32, %xmm3
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; SSE-NEXT: pmuludq %xmm4, %xmm1
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; SSE-NEXT: paddq %xmm3, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_negpow2c:
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; AVX: # %bb.0:
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; AVX-NEXT: vpbroadcastq {{.*#+}} ymm1 = [4294967295,4294967295,4294967295,4294967295]
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; AVX-NEXT: vpmuludq %ymm1, %ymm0, %ymm1
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; AVX-NEXT: vpsrlq $32, %ymm0, %ymm2
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; AVX-NEXT: vmovdqa {{.*#+}} ymm3 = [18446744073709551615,18446744073709551614,18446744073709551612,18446744073709551600]
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; AVX-NEXT: vpmuludq %ymm3, %ymm2, %ymm2
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; AVX-NEXT: vpaddq %ymm2, %ymm1, %ymm1
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; AVX-NEXT: vpsllq $32, %ymm1, %ymm1
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; AVX-NEXT: vpmuludq %ymm3, %ymm0, %ymm0
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; AVX-NEXT: vpaddq %ymm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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%1 = mul <4 x i64> %x, <i64 -1, i64 -2, i64 -4, i64 -16>
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ret <4 x i64> %1
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}
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; (mul (shl X, c1), c2) -> (mul X, c2 << c1)
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define <4 x i32> @combine_vec_mul_shl_const(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_shl_const:
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; SSE: # %bb.0:
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_shl_const:
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; AVX: # %bb.0:
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; AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %x, <i32 1, i32 2, i32 8, i32 16>
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%2 = mul <4 x i32> %1, <i32 1, i32 3, i32 5, i32 7>
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ret <4 x i32> %2
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}
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; (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one use.
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define <4 x i32> @combine_vec_mul_shl_oneuse0(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_mul_shl_oneuse0:
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; SSE: # %bb.0:
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; SSE-NEXT: pmulld %xmm1, %xmm0
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_shl_oneuse0:
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; AVX: # %bb.0:
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; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %x, <i32 1, i32 2, i32 8, i32 16>
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%2 = mul <4 x i32> %1, %y
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ret <4 x i32> %2
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}
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define <4 x i32> @combine_vec_mul_shl_oneuse1(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_mul_shl_oneuse1:
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; SSE: # %bb.0:
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; SSE-NEXT: pmulld %xmm1, %xmm0
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_shl_oneuse1:
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; AVX: # %bb.0:
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; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %x, <i32 1, i32 2, i32 8, i32 16>
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%2 = mul <4 x i32> %y, %1
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ret <4 x i32> %2
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}
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define <4 x i32> @combine_vec_mul_shl_multiuse0(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_mul_shl_multiuse0:
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; SSE: # %bb.0:
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: pmulld %xmm0, %xmm1
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; SSE-NEXT: paddd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_shl_multiuse0:
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; AVX: # %bb.0:
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; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm1
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; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %x, <i32 1, i32 2, i32 8, i32 16>
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%2 = mul <4 x i32> %1, %y
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%3 = add <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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define <4 x i32> @combine_vec_mul_shl_multiuse1(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_mul_shl_multiuse1:
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; SSE: # %bb.0:
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: pmulld %xmm0, %xmm1
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; SSE-NEXT: paddd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_shl_multiuse1:
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; AVX: # %bb.0:
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; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpmulld %xmm0, %xmm1, %xmm1
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; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %x, <i32 1, i32 2, i32 8, i32 16>
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%2 = mul <4 x i32> %y, %1
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%3 = add <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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; fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
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define <4 x i32> @combine_vec_mul_add(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_add:
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; SSE: # %bb.0:
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: paddd {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_add:
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; AVX: # %bb.0:
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; AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = add <4 x i32> %x, <i32 1, i32 2, i32 8, i32 16>
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%2 = mul <4 x i32> %1, <i32 4, i32 6, i32 2, i32 0>
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ret <4 x i32> %2
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}
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; This would infinite loop because DAGCombiner wants to turn this into a shift,
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; but x86 lowering wants to avoid non-uniform vector shift amounts.
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define <16 x i8> @PR35579(<16 x i8> %x) {
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; SSE-LABEL: PR35579:
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; SSE: # %bb.0:
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; SSE-NEXT: pmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; SSE-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
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; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
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; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
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; SSE-NEXT: pand %xmm2, %xmm0
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; SSE-NEXT: pmullw {{.*}}(%rip), %xmm1
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; SSE-NEXT: pand %xmm2, %xmm1
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; SSE-NEXT: packuswb %xmm0, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: PR35579:
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; AVX: # %bb.0:
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; AVX-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
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; AVX-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
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; AVX-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
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; AVX-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%r = mul <16 x i8> %x, <i8 0, i8 1, i8 2, i8 1, i8 4, i8 1, i8 2, i8 1, i8 8, i8 1, i8 2, i8 1, i8 4, i8 1, i8 2, i8 1>
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ret <16 x i8> %r
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}
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