forked from OSchip/llvm-project
95 lines
3.7 KiB
TableGen
95 lines
3.7 KiB
TableGen
//=- AArch64.td - Define AArch64 Combine Rules ---------------*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/GlobalISel/Combine.td"
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def fconstant_to_constant : GICombineRule<
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(defs root:$root),
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(match (wip_match_opcode G_FCONSTANT):$root,
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[{ return matchFConstantToConstant(*${root}, MRI); }]),
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(apply [{ applyFConstantToConstant(*${root}); }])>;
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def AArch64PreLegalizerCombinerHelper: GICombinerHelper<
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"AArch64GenPreLegalizerCombinerHelper", [all_combines,
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fconstant_to_constant]> {
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let DisableRuleOption = "aarch64prelegalizercombiner-disable-rule";
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let StateClass = "AArch64PreLegalizerCombinerHelperState";
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let AdditionalArguments = [];
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}
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// Matchdata for combines which replace a G_SHUFFLE_VECTOR with a
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// target-specific opcode.
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def shuffle_matchdata : GIDefMatchData<"ShuffleVectorPseudo">;
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def rev : GICombineRule<
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(defs root:$root, shuffle_matchdata:$matchinfo),
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchREV(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
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>;
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def zip : GICombineRule<
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(defs root:$root, shuffle_matchdata:$matchinfo),
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchZip(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
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>;
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def uzp : GICombineRule<
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(defs root:$root, shuffle_matchdata:$matchinfo),
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchUZP(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
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>;
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def dup: GICombineRule <
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(defs root:$root, shuffle_matchdata:$matchinfo),
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchDup(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
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>;
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def trn : GICombineRule<
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(defs root:$root, shuffle_matchdata:$matchinfo),
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchTRN(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
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>;
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def ext: GICombineRule <
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(defs root:$root, shuffle_matchdata:$matchinfo),
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchEXT(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyEXT(*${root}, ${matchinfo}); }])
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>;
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// Combines which replace a G_SHUFFLE_VECTOR with a target-specific pseudo
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// instruction.
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def shuffle_vector_pseudos : GICombineGroup<[dup, rev, ext, zip, uzp, trn]>;
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def vashr_vlshr_imm_matchdata : GIDefMatchData<"int64_t">;
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def vashr_vlshr_imm : GICombineRule<
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(defs root:$root, vashr_vlshr_imm_matchdata:$matchinfo),
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(match (wip_match_opcode G_ASHR, G_LSHR):$root,
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[{ return matchVAshrLshrImm(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyVAshrLshrImm(*${root}, MRI, ${matchinfo}); }])
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>;
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def AArch64PostLegalizerCombinerHelper
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: GICombinerHelper<"AArch64GenPostLegalizerCombinerHelper",
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[copy_prop, erase_undef_store, combines_for_extload,
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sext_trunc_sextload, shuffle_vector_pseudos,
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hoist_logic_op_with_same_opcode_hands,
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and_trivial_mask, vashr_vlshr_imm, xor_of_and_with_same_reg]> {
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let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule";
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}
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