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llvm-project/llvm/lib/Target/AArch64
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Evgenii Stepanov 188a7d6710 Add alloca size threshold for StackTagging initializer merging. 
Summary:
Initializer merging generates pretty inefficient code for large allocas
that also happens to trigger an exponential algorithm somewhere in
Machine Instruction Scheduler. See https://bugs.llvm.org/show_bug.cgi?id=47867.

This change adds an upper limit for the alloca size. The default limit
is selected such that worst case size of memtag-generated code is
similar to non-memtag (but because of the ISA quirks, this case is
realized at the different value of alloca size, ex. memset inlining
triggers at sizes below 512, but stack tagging instructions are 2x
shorter, so limit is approx. 256).

We could try harder to emit more compact code with initializer merging,
but that would only affect large, sparsely initialized allocas, and
those are doing fine already.

Reviewers: vitalybuka, pcc

Subscribers: llvm-commits
 		2020-10-19 13:44:07 -07:00
..
AsmParser [AArch64] Implement .variant_pcs directive 2020-10-13 10:06:27 +00:00
Disassembler [AArch64] Emit warning when disassembling unpredictable LDRAA and LDRAB 2020-06-25 15:56:36 +01:00
GISel [AArch64][GlobalISel] Select csinc if a select has a 1 on RHS. 2020-10-16 16:49:52 -07:00
MCTargetDesc [AArch64] Implement .variant_pcs directive 2020-10-13 10:06:27 +00:00
TargetInfo
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Utils [ARM, AArch64] Fix a comment typo. NFC. 2020-08-06 09:23:45 +03:00
AArch64.h [AArch64] Extend AArch64SLSHardeningPass to harden BLR instructions. 2020-06-12 07:34:33 +01:00
AArch64.td [AArch64] Add CPU Cortex-R82 2020-10-02 12:47:23 +01:00
AArch64A53Fix835769.cpp
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AArch64A57FPLoadBalancing.cpp
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AArch64AdvSIMDScalarPass.cpp [AArch64] Update a code comment incorrectly referring to zero_reg. NFC 2020-08-20 14:36:59 +02:00
AArch64AsmPrinter.cpp [AArch64] Implement .variant_pcs directive 2020-10-13 10:06:27 +00:00
AArch64BranchTargets.cpp [AArch64] PAC/BTI code generation for LLVM generated functions 2020-09-25 11:47:14 +01:00
AArch64CallingConvention.cpp [SVE] Add fatal error when running out of registers for SVE tuple call arguments 2020-10-14 09:31:41 +01:00
AArch64CallingConvention.h
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AArch64CallingConvention.td [Alignment][NFC] Use Align for TargetCallingConv::OrigAlign 2020-06-25 13:21:22 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
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AArch64CollectLOH.cpp [AArch64] Fix CollectLOH creating an AdrpAdd LOH when there's a live used reg 2020-06-01 16:00:55 -07:00
AArch64Combine.td [GlobalISel] Combine (xor (and x, y), y) -> (and (not x), y) 2020-09-28 10:08:14 -07:00
AArch64CompressJumpTables.cpp
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AArch64CondBrTuning.cpp
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AArch64ConditionOptimizer.cpp MachineBasicBlock::updateTerminator now requires an explicit layout successor. 2020-06-06 22:30:51 -04:00
AArch64ConditionalCompares.cpp DomTree: Remove getChildren() accessor 2020-07-06 21:58:11 +02:00
AArch64DeadRegisterDefinitionsPass.cpp
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AArch64ExpandImm.cpp
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AArch64ExpandImm.h
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AArch64ExpandPseudoInsts.cpp [SVE] Fix invalid assert in expand_DestructiveOp. 2020-07-04 09:21:40 +00:00
AArch64FalkorHWPFFix.cpp Small fixes for "[LoopInfo] empty() -> isInnermost(), add isOutermost()" 2020-09-22 23:59:34 +03:00
AArch64FastISel.cpp [FastISel] update to use intrinsic's isCommutative(); NFC 2020-08-30 11:36:41 -04:00
AArch64FrameLowering.cpp [AArch64] Stack frame reordering. 2020-10-15 12:50:16 -07:00
AArch64FrameLowering.h [AArch64] Stack frame reordering. 2020-10-15 12:50:16 -07:00
AArch64GenRegisterBankInfo.def
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AArch64ISelDAGToDAG.cpp [AArch64] PAC/BTI code generation for LLVM generated functions 2020-09-25 11:47:14 +01:00
AArch64ISelLowering.cpp [SVE][AArch64] Replace TypeSize comparisons with their integer equivalents 2020-10-19 07:41:33 +01:00
AArch64ISelLowering.h [AArch64] Identify SAD pattern 2020-10-13 15:50:54 +05:30
AArch64InstrAtomics.td
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AArch64InstrFormats.td [SVE][CodeGen] Lower scalable fp_extend & fp_round operations 2020-10-01 12:17:37 +01:00
AArch64InstrGISel.td [AArch64][GlobalISel] Add a post-legalize combine for lowering vector-immediate G_ASHR/G_LSHR. 2020-09-21 16:04:52 -07:00
AArch64InstrInfo.cpp [ImplicitNullChecks] Support complex addressing mode 2020-10-07 20:55:38 -04:00
AArch64InstrInfo.h [ImplicitNullChecks] Support complex addressing mode 2020-10-07 20:55:38 -04:00
AArch64InstrInfo.td [AArch64] Identify SAD pattern 2020-10-13 15:50:54 +05:30
AArch64LoadStoreOptimizer.cpp [AArch64] Don't merge sp decrement into later stores when using WinCFI 2020-10-01 19:03:27 +03:00
AArch64MCInstLower.cpp
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AArch64MCInstLower.h
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AArch64MachineFunctionInfo.cpp [AArch64] PAC/BTI code generation for LLVM generated functions 2020-09-25 11:47:14 +01:00
AArch64MachineFunctionInfo.h [MTE] Pin the tagged base pointer to one of the stack slots. 2020-10-15 12:50:16 -07:00
AArch64MacroFusion.cpp
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AArch64MacroFusion.h
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AArch64PBQPRegAlloc.cpp
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AArch64PBQPRegAlloc.h
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AArch64PerfectShuffle.h
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AArch64PfmCounters.td
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AArch64PromoteConstant.cpp [AArch64] Don't promote constants with float ConstantExpr. 2020-05-13 23:31:47 +01:00
AArch64RedundantCopyElimination.cpp
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AArch64RegisterBanks.td
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AArch64RegisterInfo.cpp [AArch64] Statepoint support for AArch64. 2020-09-14 16:43:08 -07:00
AArch64RegisterInfo.h [AARCH64][RegisterCoalescer] clang miscompiles zero-extension to long long 2020-09-08 08:04:52 +01:00
AArch64RegisterInfo.td [AArch64][SVE] Fix CFA calculation in presence of SVE objects. 2020-08-04 11:47:06 +01:00
AArch64SIMDInstrOpt.cpp [AArch64] reuse another map iterator. NFC 2020-09-28 11:30:21 -07:00
AArch64SLSHardening.cpp [NFC] Clean up uses of MachineModuleInfoWrapperPass 2020-07-01 09:45:05 -07:00
AArch64SVEInstrInfo.td [SVE] Add ISel patterns for "insert undef_nxv#f##, f##, 0" 2020-10-13 10:49:18 +01:00
AArch64SchedA53.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedA55.td [AArch64] Cortex-A55 scheduler model 2020-09-21 10:54:32 +01:00
AArch64SchedA57.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedA57WriteRes.td
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AArch64SchedCyclone.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedExynosM3.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedExynosM4.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedExynosM5.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedFalkor.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedFalkorDetails.td
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AArch64SchedKryo.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedKryoDetails.td
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AArch64SchedPredExynos.td
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AArch64SchedPredicates.td
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AArch64SchedThunderX.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedThunderX2T99.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedThunderX3T110.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64Schedule.td
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AArch64SelectionDAGInfo.cpp [CodeGen] Refactor getMemBasePlusOffset & getObjectPtrOffset to accept a TypeSize 2020-08-11 12:17:10 +01:00
AArch64SelectionDAGInfo.h [Alignment][NFC] Migrate SelectionDAGTargetInfo::EmitTargetCodeForMemset to Align 2020-06-30 12:46:26 +00:00
AArch64SpeculationHardening.cpp
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AArch64StackOffset.h [AArch64][SVE] Fix CFA calculation in presence of SVE objects. 2020-08-04 11:47:06 +01:00
AArch64StackTagging.cpp Add alloca size threshold for StackTagging initializer merging. 2020-10-19 13:44:07 -07:00
AArch64StackTaggingPreRA.cpp [MTE] Pin the tagged base pointer to one of the stack slots. 2020-10-15 12:50:16 -07:00
AArch64StorePairSuppress.cpp
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AArch64Subtarget.cpp [AArch64] Add CPU Cortex-R82 2020-10-02 12:47:23 +01:00
AArch64Subtarget.h [AArch64] Add CPU Cortex-R82 2020-10-02 12:47:23 +01:00
AArch64SystemOperands.td [AArch64] Add CPU Cortex-R82 2020-10-02 12:47:23 +01:00
AArch64TargetMachine.cpp [GlobalISel] Enable usage of BranchProbabilityInfo in IRTranslator. 2020-09-09 14:31:12 -07:00
AArch64TargetMachine.h Support addrspacecast initializers with isNoopAddrSpaceCast 2020-07-31 10:42:43 -04:00
AArch64TargetObjectFile.cpp
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AArch64TargetObjectFile.h [llvm][ELF][AArch64] Handle R_AARCH64_PLT32 relocation 2020-06-10 11:34:16 -07:00
AArch64TargetTransformInfo.cpp [SVE][AArch64] Replace TypeSize comparisons with their integer equivalents 2020-10-19 07:41:33 +01:00
AArch64TargetTransformInfo.h [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
CMakeLists.txt [AArch64] Introduce AArch64SLSHardeningPass, implementing hardening of RET and BR instructions. 2020-06-11 07:51:17 +01:00
LLVMBuild.txt
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SVEInstrFormats.td [Aarch64] [TableGen] Clean up !if(!eq(boolean, 1) and related booleans. 2020-10-19 10:33:55 -04:00
SVEIntrinsicOpts.cpp [SVE] Fix bug in SVEIntrinsicOpts::optimizePTest 2020-08-14 07:57:21 +01:00