forked from OSchip/llvm-project
210 lines
6.5 KiB
LLVM
210 lines
6.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+ssse3 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2
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; Verify that the following shifts are lowered into a sequence of two shifts plus
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; a blend. On pre-avx2 targets, instead of scalarizing logical and arithmetic
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; packed shift right by a constant build_vector the backend should always try to
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; emit a simpler sequence of two shifts + blend when possible.
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define <8 x i16> @test1(<8 x i16> %a) {
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; SSE-LABEL: test1:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrlw $3, %xmm1
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; SSE-NEXT: psrlw $2, %xmm0
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; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test1:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrlw $3, %xmm0, %xmm1
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; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test1:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsrlw $3, %xmm0, %xmm1
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; AVX2-NEXT: vpsrlw $2, %xmm0, %xmm0
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; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; AVX2-NEXT: retq
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%lshr = lshr <8 x i16> %a, <i16 3, i16 3, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
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ret <8 x i16> %lshr
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}
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define <8 x i16> @test2(<8 x i16> %a) {
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; SSE-LABEL: test2:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrlw $3, %xmm1
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; SSE-NEXT: psrlw $2, %xmm0
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; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test2:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm1
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; AVX1-NEXT: vpsrlw $3, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test2:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsrlw $2, %xmm0, %xmm1
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; AVX2-NEXT: vpsrlw $3, %xmm0, %xmm0
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; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX2-NEXT: retq
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%lshr = lshr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 2, i16 2, i16 2, i16 2>
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ret <8 x i16> %lshr
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}
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define <4 x i32> @test3(<4 x i32> %a) {
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; SSE-LABEL: test3:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrld $3, %xmm1
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; SSE-NEXT: psrld $2, %xmm0
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; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test3:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrld $3, %xmm0, %xmm1
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; AVX1-NEXT: vpsrld $2, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test3:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX2-NEXT: retq
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%lshr = lshr <4 x i32> %a, <i32 3, i32 2, i32 2, i32 2>
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ret <4 x i32> %lshr
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}
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define <4 x i32> @test4(<4 x i32> %a) {
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; SSE-LABEL: test4:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrld $3, %xmm1
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; SSE-NEXT: psrld $2, %xmm0
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; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test4:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrld $2, %xmm0, %xmm1
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; AVX1-NEXT: vpsrld $3, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test4:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX2-NEXT: retq
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%lshr = lshr <4 x i32> %a, <i32 3, i32 3, i32 2, i32 2>
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ret <4 x i32> %lshr
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}
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define <8 x i16> @test5(<8 x i16> %a) {
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; SSE-LABEL: test5:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psraw $3, %xmm1
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; SSE-NEXT: psraw $2, %xmm0
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; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test5:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsraw $3, %xmm0, %xmm1
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; AVX1-NEXT: vpsraw $2, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test5:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsraw $3, %xmm0, %xmm1
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; AVX2-NEXT: vpsraw $2, %xmm0, %xmm0
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; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; AVX2-NEXT: retq
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%lshr = ashr <8 x i16> %a, <i16 3, i16 3, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
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ret <8 x i16> %lshr
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}
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define <8 x i16> @test6(<8 x i16> %a) {
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; SSE-LABEL: test6:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psraw $3, %xmm1
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; SSE-NEXT: psraw $2, %xmm0
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; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test6:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsraw $2, %xmm0, %xmm1
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; AVX1-NEXT: vpsraw $3, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test6:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsraw $2, %xmm0, %xmm1
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; AVX2-NEXT: vpsraw $3, %xmm0, %xmm0
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; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX2-NEXT: retq
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%lshr = ashr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 2, i16 2, i16 2, i16 2>
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ret <8 x i16> %lshr
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}
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define <4 x i32> @test7(<4 x i32> %a) {
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; SSE-LABEL: test7:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrad $3, %xmm1
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; SSE-NEXT: psrad $2, %xmm0
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; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test7:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrad $3, %xmm0, %xmm1
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; AVX1-NEXT: vpsrad $2, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test7:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
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; AVX2-NEXT: retq
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%lshr = ashr <4 x i32> %a, <i32 3, i32 2, i32 2, i32 2>
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ret <4 x i32> %lshr
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}
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define <4 x i32> @test8(<4 x i32> %a) {
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; SSE-LABEL: test8:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrad $3, %xmm1
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; SSE-NEXT: psrad $2, %xmm0
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; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test8:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrad $2, %xmm0, %xmm1
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; AVX1-NEXT: vpsrad $3, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test8:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
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; AVX2-NEXT: retq
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%lshr = ashr <4 x i32> %a, <i32 3, i32 3, i32 2, i32 2>
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ret <4 x i32> %lshr
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}
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