forked from OSchip/llvm-project
177 lines
3.4 KiB
LLVM
177 lines
3.4 KiB
LLVM
; RUN: llc -march=mipsel < %s | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic < %s -asm-show-inst | FileCheck %s -check-prefix=MMR6
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@g1 = external global i32
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; CHECK-LABEL: seteq0:
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; CHECK: sltiu ${{[0-9]+}}, $4, 1
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; MMR6: sltiu ${{[0-9]+}}, $4, 1
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; MMR6: <MCInst #{{[0-9]+}} SLTiu_MM
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define i32 @seteq0(i32 %a) {
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entry:
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%cmp = icmp eq i32 %a, 0
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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; CHECK-LABEL: setne0:
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; CHECK: sltu ${{[0-9]+}}, $zero, $4
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; MMR6: sltu ${{[0-9]+}}, $zero, $4
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; MMR6: <MCInst #{{[0-9]+}} SLTu_MM
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define i32 @setne0(i32 %a) {
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entry:
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%cmp = icmp ne i32 %a, 0
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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; CHECK-LABEL: slti_beq0:
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; CHECK: slti $[[R0:[0-9]+]], $4, -32768
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; MMR6: slti $[[R0:[0-9]+]], $4, -32768
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; MMR6: <MCInst #{{[0-9]+}} SLTi_MM
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; CHECK: beqz $[[R0]]
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define void @slti_beq0(i32 %a) {
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entry:
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%cmp = icmp slt i32 %a, -32768
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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store i32 %a, i32* @g1, align 4
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br label %if.end
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if.end:
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ret void
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}
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; CHECK-LABEL: slti_beq1:
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; CHECK: slt ${{[0-9]+}}
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; MMR6: slt ${{[0-9]+}}
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; MMR6: <MCInst #{{[0-9]+}} SLT_MM
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define void @slti_beq1(i32 %a) {
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entry:
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%cmp = icmp slt i32 %a, -32769
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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store i32 %a, i32* @g1, align 4
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br label %if.end
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if.end:
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ret void
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}
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; CHECK-LABEL: slti_beq2:
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; CHECK: slti $[[R0:[0-9]+]], $4, 32767
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; MMR6: slti $[[R0:[0-9]+]], $4, 32767
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; MMR6: <MCInst #{{[0-9]+}} SLTi_MM
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; CHECK: beqz $[[R0]]
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define void @slti_beq2(i32 %a) {
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entry:
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%cmp = icmp slt i32 %a, 32767
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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store i32 %a, i32* @g1, align 4
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br label %if.end
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if.end:
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ret void
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}
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; CHECK-LABEL: slti_beq3:
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; CHECK: slt ${{[0-9]+}}
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; MMR6: slt ${{[0-9]+}}
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; MMR6: <MCInst #{{[0-9]+}} SLT_MM
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define void @slti_beq3(i32 %a) {
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entry:
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%cmp = icmp slt i32 %a, 32768
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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store i32 %a, i32* @g1, align 4
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br label %if.end
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if.end:
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ret void
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}
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; CHECK-LABEL: sltiu_beq0:
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; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
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; MMR6: sltiu $[[R0:[0-9]+]], $4, 32767
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; MMR6: <MCInst #{{[0-9]+}} SLTiu_MM
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; CHECK: beqz $[[R0]]
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define void @sltiu_beq0(i32 %a) {
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entry:
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%cmp = icmp ult i32 %a, 32767
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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store i32 %a, i32* @g1, align 4
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br label %if.end
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if.end:
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ret void
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}
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; CHECK-LABEL: sltiu_beq1:
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; CHECK: sltu ${{[0-9]+}}
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; MMR6: sltu ${{[0-9]+}}
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; MMR6: <MCInst #{{[0-9]+}} SLTu_MM
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define void @sltiu_beq1(i32 %a) {
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entry:
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%cmp = icmp ult i32 %a, 32768
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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store i32 %a, i32* @g1, align 4
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br label %if.end
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if.end:
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ret void
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}
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; CHECK-LABEL: sltiu_beq2:
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; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
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; MMR6: sltiu $[[R0:[0-9]+]], $4, -32768
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; MMR6: <MCInst #{{[0-9]+}} SLTiu_MM
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; CHECK: beqz $[[R0]]
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define void @sltiu_beq2(i32 %a) {
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entry:
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%cmp = icmp ult i32 %a, -32768
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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store i32 %a, i32* @g1, align 4
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br label %if.end
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if.end:
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ret void
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}
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; CHECK-LABEL: sltiu_beq3:
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; CHECK: sltu ${{[0-9]+}}
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; MMR6: sltu ${{[0-9]+}}
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; MMR6: <MCInst #{{[0-9]+}} SLTu_MM
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define void @sltiu_beq3(i32 %a) {
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entry:
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%cmp = icmp ult i32 %a, -32769
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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store i32 %a, i32* @g1, align 4
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br label %if.end
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if.end:
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ret void
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}
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