forked from OSchip/llvm-project
176 lines
5.8 KiB
YAML
176 lines
5.8 KiB
YAML
# Basic machine sched model test for Thumb2 int instructions
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# RUN: llc -o /dev/null %s -mtriple=thumbv7-eabi -mcpu=swift -run-pass machine-scheduler -enable-misched -verify-misched \
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# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT
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# RUN: llc -o /dev/null %s -mtriple=thumbv7--eabi -mcpu=cortex-a9 -run-pass machine-scheduler -enable-misched -verify-misched \
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# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9
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# RUN: llc -o /dev/null %s -mtriple=thumbv8r-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -verify-misched \
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# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52
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# REQUIRES: asserts
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--- |
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; ModuleID = 'foo.ll'
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source_filename = "foo.ll"
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv7---eabi"
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@g1 = common global i32 0, align 4
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@g2 = common global i32 0, align 4
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define i64 @foo(i16 signext %a, i16 signext %b) {
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entry:
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%0 = load i32, i32* @g1, align 4
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%1 = load i32, i32* @g2, align 4
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%2 = add nuw nsw i32 %0, %0
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%3 = sdiv i32 %2, %1
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store i32 %3, i32* @g1, align 4
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%d = mul nsw i16 %a, %a
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%e = mul nsw i16 %b, %b
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%f = add nuw nsw i16 %e, %d
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%c = zext i16 %f to i32
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%mul8 = mul nsw i32 %c, %3
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%mul9 = mul nsw i32 %mul8, %mul8
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%add10 = add nuw nsw i32 %mul9, %mul8
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%conv1130 = zext i32 %add10 to i64
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%mul12 = mul nuw nsw i64 %conv1130, %conv1130
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%mul13 = mul nsw i64 %mul12, %mul12
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%add14 = add nuw nsw i64 %mul13, %mul12
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ret i64 %add14
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}
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#
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# CHECK: ********** MI Scheduling **********
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# CHECK: SU(2): %2:rgpr = t2MOVi32imm @g1
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# CHECK_A9: Latency : 2
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# CHECK_SWIFT: Latency : 2
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# CHECK_R52: Latency : 2
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#
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# CHECK: SU(3): %3:rgpr = t2LDRi12 %2:rgpr, 0, 14, %noreg; mem:LD4[@g1](dereferenceable)
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# CHECK_A9: Latency : 1
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# CHECK_SWIFT: Latency : 3
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# CHECK_R52: Latency : 4
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#
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# CHECK : SU(6): %6 = t2ADDrr %3:rgpr, %3:rgpr, 14, %noreg, %noreg
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# CHECK_A9: Latency : 1
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# CHECK_SWIFT: Latency : 1
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# CHECK_R52: Latency : 3
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# CHECK: SU(7): %7:rgpr = t2SDIV %6:rgpr, %5:rgpr, 14, %noreg
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# CHECK_A9: Latency : 0
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# CHECK_SWIFT: Latency : 14
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# CHECK_R52: Latency : 8
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# CHECK: SU(8): t2STRi12 %7:rgpr, %2:rgpr, 0, 14, %noreg; mem:ST4[@g1]
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# CHECK_A9: Latency : 1
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# CHECK_SWIFT: Latency : 0
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# CHECK_R52: Latency : 4
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#
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# CHECK: SU(9): %8:rgpr = t2SMULBB %1:rgpr, %1:rgpr, 14, %noreg
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# CHECK_A9: Latency : 2
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# CHECK_SWIFT: Latency : 4
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# CHECK_R52: Latency : 4
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#
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# CHECK: SU(10): %9:rgpr = t2SMLABB %0:rgpr, %0:rgpr, %8:rgpr, 14, %noreg
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# CHECK_A9: Latency : 2
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# CHECK_SWIFT: Latency : 4
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# CHECK_R52: Latency : 4
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#
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# CHECK: SU(11): %10:rgpr = t2UXTH %9:rgpr, 0, 14, %noreg
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# CHECK_A9: Latency : 1
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# CHECK_SWIFT: Latency : 1
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# CHECK_R52: Latency : 3
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#
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# CHECK: SU(12): %11:rgpr = t2MUL %10:rgpr, %7:rgpr, 14, %noreg
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# CHECK_A9: Latency : 2
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# CHECK_SWIFT: Latency : 4
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# CHECK_R52: Latency : 4
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#
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# CHECK: SU(13): %12:rgpr = t2MLA %11:rgpr, %11:rgpr, %11:rgpr, 14, %noreg
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# CHECK_A9: Latency : 2
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# CHECK_SWIFT: Latency : 4
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# CHECK_R52: Latency : 4
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#
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# CHECK: SU(14): %13:rgpr, %14:rgpr = t2UMULL %12:rgpr, %12:rgpr, 14, %noreg
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# CHECK_A9: Latency : 3
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# CHECK_SWIFT: Latency : 5
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# CHECK_R52: Latency : 4
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#
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# CHECK: SU(18): %19:rgpr, %20:rgpr = t2UMLAL %12:rgpr, %12:rgpr, %19:rgpr, %20:rgpr, 14, %noreg
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# CHECK_A9: Latency : 3
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# CHECK_SWIFT: Latency : 7
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# CHECK_R52: Latency : 4
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# CHECK: ** ScheduleDAGMILive::schedule picking next node
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...
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---
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name: foo
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: rgpr }
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- { id: 1, class: rgpr }
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- { id: 2, class: rgpr }
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- { id: 3, class: rgpr }
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- { id: 4, class: rgpr }
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- { id: 5, class: rgpr }
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- { id: 6, class: rgpr }
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- { id: 7, class: rgpr }
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- { id: 8, class: rgpr }
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- { id: 9, class: rgpr }
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- { id: 10, class: rgpr }
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- { id: 11, class: rgpr }
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- { id: 12, class: rgpr }
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- { id: 13, class: rgpr }
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- { id: 14, class: rgpr }
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- { id: 15, class: rgpr }
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- { id: 16, class: rgpr }
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- { id: 17, class: rgpr }
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- { id: 18, class: rgpr }
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- { id: 19, class: rgpr }
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- { id: 20, class: rgpr }
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liveins:
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- { reg: '%r0', virtual-reg: '%0' }
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- { reg: '%r1', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0.entry:
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liveins: %r0, %r1
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%1 = COPY %r1
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%0 = COPY %r0
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%2 = t2MOVi32imm @g1
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%3 = t2LDRi12 %2, 0, 14, %noreg :: (dereferenceable load 4 from @g1)
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%4 = t2MOVi32imm @g2
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%5 = t2LDRi12 %4, 0, 14, %noreg :: (dereferenceable load 4 from @g2)
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%6 = t2ADDrr %3, %3, 14, %noreg, %noreg
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%7 = t2SDIV %6, %5, 14, %noreg
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t2STRi12 %7, %2, 0, 14, %noreg :: (store 4 into @g1)
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%8 = t2SMULBB %1, %1, 14, %noreg
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%9 = t2SMLABB %0, %0, %8, 14, %noreg
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%10 = t2UXTH %9, 0, 14, %noreg
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%11 = t2MUL %10, %7, 14, %noreg
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%12 = t2MLA %11, %11, %11, 14, %noreg
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%13, %14 = t2UMULL %12, %12, 14, %noreg
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%19, %16 = t2UMULL %13, %13, 14, %noreg
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%17 = t2MLA %13, %14, %16, 14, %noreg
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%20 = t2MLA %13, %14, %17, 14, %noreg
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%19, %20 = t2UMLAL %12, %12, %19, %20, 14, %noreg
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%r0 = COPY %19
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%r1 = COPY %20
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tBX_RET 14, %noreg, implicit %r0, implicit %r1
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...
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