forked from OSchip/llvm-project
120 lines
4.0 KiB
C++
120 lines
4.0 KiB
C++
//===- PPCMachineScheduler.cpp - MI Scheduler for PowerPC -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "PPCMachineScheduler.h"
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#include "MCTargetDesc/PPCMCTargetDesc.h"
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using namespace llvm;
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static cl::opt<bool>
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DisableAddiLoadHeuristic("disable-ppc-sched-addi-load",
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cl::desc("Disable scheduling addi instruction before"
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"load for ppc"), cl::Hidden);
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static cl::opt<bool>
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EnableAddiHeuristic("ppc-postra-bias-addi",
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cl::desc("Enable scheduling addi instruction as early"
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"as possible post ra"),
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cl::Hidden, cl::init(true));
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static bool isADDIInstr(const GenericScheduler::SchedCandidate &Cand) {
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return Cand.SU->getInstr()->getOpcode() == PPC::ADDI ||
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Cand.SU->getInstr()->getOpcode() == PPC::ADDI8;
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}
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bool PPCPreRASchedStrategy::biasAddiLoadCandidate(SchedCandidate &Cand,
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SchedCandidate &TryCand,
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SchedBoundary &Zone) const {
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if (DisableAddiLoadHeuristic)
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return false;
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SchedCandidate &FirstCand = Zone.isTop() ? TryCand : Cand;
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SchedCandidate &SecondCand = Zone.isTop() ? Cand : TryCand;
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if (isADDIInstr(FirstCand) && SecondCand.SU->getInstr()->mayLoad()) {
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TryCand.Reason = Stall;
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return true;
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}
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if (FirstCand.SU->getInstr()->mayLoad() && isADDIInstr(SecondCand)) {
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TryCand.Reason = NoCand;
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return true;
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}
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return false;
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}
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void PPCPreRASchedStrategy::tryCandidate(SchedCandidate &Cand,
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SchedCandidate &TryCand,
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SchedBoundary *Zone) const {
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GenericScheduler::tryCandidate(Cand, TryCand, Zone);
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if (!Cand.isValid() || !Zone)
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return;
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// Add powerpc specific heuristic only when TryCand isn't selected or
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// selected as node order.
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if (TryCand.Reason != NodeOrder && TryCand.Reason != NoCand)
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return;
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// There are some benefits to schedule the ADDI before the load to hide the
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// latency, as RA may create a true dependency between the load and addi.
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if (biasAddiLoadCandidate(Cand, TryCand, *Zone))
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return;
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}
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bool PPCPostRASchedStrategy::biasAddiCandidate(SchedCandidate &Cand,
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SchedCandidate &TryCand) const {
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if (!EnableAddiHeuristic)
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return false;
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if (isADDIInstr(TryCand) && !isADDIInstr(Cand)) {
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TryCand.Reason = Stall;
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return true;
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}
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return false;
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}
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void PPCPostRASchedStrategy::tryCandidate(SchedCandidate &Cand,
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SchedCandidate &TryCand) {
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PostGenericScheduler::tryCandidate(Cand, TryCand);
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if (!Cand.isValid())
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return;
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// Add powerpc post ra specific heuristic only when TryCand isn't selected or
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// selected as node order.
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if (TryCand.Reason != NodeOrder && TryCand.Reason != NoCand)
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return;
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// There are some benefits to schedule the ADDI as early as possible post ra
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// to avoid stalled by vector instructions which take up all the hw units.
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// And ADDI is usually used to post inc the loop indvar, which matters the
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// performance.
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if (biasAddiCandidate(Cand, TryCand))
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return;
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}
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void PPCPostRASchedStrategy::enterMBB(MachineBasicBlock *MBB) {
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// Custom PPC PostRA specific behavior here.
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PostGenericScheduler::enterMBB(MBB);
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}
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void PPCPostRASchedStrategy::leaveMBB() {
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// Custom PPC PostRA specific behavior here.
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PostGenericScheduler::leaveMBB();
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}
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void PPCPostRASchedStrategy::initialize(ScheduleDAGMI *Dag) {
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// Custom PPC PostRA specific initialization here.
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PostGenericScheduler::initialize(Dag);
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}
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SUnit *PPCPostRASchedStrategy::pickNode(bool &IsTopNode) {
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// Custom PPC PostRA specific scheduling here.
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return PostGenericScheduler::pickNode(IsTopNode);
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}
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