Greg Clayton 6da4ca83b0 Added the start of opcode emulation for ARM instructions. This class is designed ... to be fed 4 callbacks: read/write memory, and read/write registers. After this, you can tell the object to read an instruction. This will cause the class to read the PC, and read and instruction. Then you can emulate the instruction by calling EvaluateInstruction. This will cause the class to figure out exactly what an opcode does, and call the read/write mem/regs functions with actual values which allows one to emulate an instruction without running a process, or it allows one to watch the context information (the memory write is a pushing register 3 onto the stack at offset 12) so it can be used for generating call frame information. This way, in the future, we will have one class that can be used to emulate instructions and generate our unwind info from assembly. llvm-svn: 123998		2011-01-21 22:02:52 +00:00
clang	Generalize the NRVO move-construction-based initialization routine. No functionality change	2011-01-21 21:08:57 +00:00
compiler-rt	clang_darwin: We don't need clear_cache for use with Clang on ARM/Darwin.	2011-01-21 18:23:47 +00:00
debuginfo-tests	Test case for r123199.	2011-01-11 00:31:01 +00:00
libcxx	Add attribute to inlined member.	2011-01-13 20:05:05 +00:00
lldb	Added the start of opcode emulation for ARM instructions. This class is designed	2011-01-21 22:02:52 +00:00
llvm	Sparc backend:	2011-01-21 22:00:00 +00:00